參數(shù)資料
型號: DDC118
英文描述: Octal Current Input 20-Bit Analog-To-Digital Converter
中文描述: 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 24/30頁
文件大?。?/td> 384K
代理商: DDC118
""#
SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
24
RETRIEVAL
AFTER
CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t
29
after CONV
toggles before beginning. See Figure 24 for an example of
this. The maximum time available for retrieval is
t
27
t
29
– t
26
(344.875
μ
s – 10
μ
s – 1.75
μ
s for
CLK = 4MHz), regardless of T
INT
. The maximum number
of DDC118s that can be daisy-chained together (FORMAT
= high) is calculated by Equation 3:
333.125 s
160
DCLK
NOTE: 128
τ
DCLK
is used for FORMAT = low.
For DCLK = 10MHz, the maximum number of DDC118s is
20 (or 26 for FORMAT = low).
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
MIN
TYP
1.75
345.00
±
0.125
10
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
1.458
287.5
±
0.104
10
UNITS
MAX
MAX
t26
t27
t29
Hold Time that DOUT is Valid Before Falling Edge of DVALID
μ
s
μ
s
μ
s
Cont Mode Data Ready
Data Retrieval Start-Up After Edge of CONV
Figure 24. Readback
After
CONV Toggles
(3)
T
INT
t
27
t
t
26
T
INT
T
INT
Side A
Data
Side B
Data
Side A
Data
CONV
DVALID
DCLK
DOUT
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