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參數(shù)資料
| 型號： | DDC118 |
| 英文描述： | Octal Current Input 20-Bit Analog-To-Digital Converter |
| 中文描述： | 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 384K |
| 代理商： | DDC118 |
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SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
21
DATA FORMAT (FORMAT)
The serial output data is provided in an offset binary code
as shown in Table 9. The digital input pin FORMAT selects
how many bits are used in the output word. When
FORMAT is high (1), 20 bits are used. When FORMAT is
low (0), the lower 4 bits are truncated so that only 16 bits
are used. Note that the LSB size is 16 times bigger when
FORMAT = 0. An offset is included in the output to allow
slightly negative inputs, from board leakages for example,
from clipping the reading. This offset is approximately
0.4% of the positive full-scale.
Table 9. Ideal Output Code
(1)
vs Input Signal
INPUT
SIGNAL
FORMAT = HIGH
(1)
IDEAL OUTPUT CODE
IDEAL OUTPUT CODE
FORMAT = LOW
(0)
≥
100% FS
1111 1111 1111 1111 1111
1111 1111 1111 1111
0.001531% FS
0000 0001 0000 0001 0000
0000 0001 0000 0001
0.001436% FS
0000 0001 0000 0000 1111
0000 0001 0000 0000
0.000191% FS
0000 0001 0000 0000 0010
0000 0001 0000 0000
0.000096% FS
0000 0001 0000 0000 0001
0000 0001 0000 0000
0% FS
0000 0001 0000 0000 0000
0000 0001 0000 0000
0.3955% FS
(1)Excludes the effects of noise, INL, offset, and gain errors.
0000 0000 0000 0000 0000
0000 0000 0000 0000
DATA RETRIEVAL
In both the continuous and non-continuous modes of
operation, the data from the last conversion is available for
retrieval on the falling edge of DVALID (see Figure 20 and
Table 10). Data is shifted out on the falling edge of the data
clock, DCLK. Make sure not to retrieve data while CONV
changes as this can introduce noise. Stop activity on
DCLK at least 10
μ
s before or after a CONV transition.
Setting the FORMAT pin = 0 (16-bit output word) reduces
the time needed to retrieve data by 20%, since there are
fewer bits to shift out. This time reduction can be useful in
multichannel systems requiring only 16 bits of resolution.
CLK
DVALID
DCLK
DOUT
t
18
t
19
t
21
t
20
Input 8
MSB
Input 1
LSB
Input 8
LSB
Input 7
MSB
Input 5
LSB
Input 4
MSB
Input 2
LSB
Input 1
MSB
Input 8
MSB
t
20
Figure 20. Digital Interface Timing Diagram for Data Retrieval From a Single DDC118
Table 10. Timing for the DDC118 Data Retrieval
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
MIN
TYP
5
5
1.75
5
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
5
5
1.458
5
UNITS
MAX
MAX
t18
t19
t20
t21
Propagation Delay from Falling Edge of CLK to DVALID LOW
Propagation Delay from Falling Edge of DCLK to DVALID HIGH
Hold Time that DOUT is Valid Before the Falling Edge of DVALID
Hold Time that DOUT is Valid After Falling Edge of DCLK
Propagation Delay from Falling Edge of DCLK to Valid DOUT
(1)
With a maximum load of one DDC118 (4pF typical) with an additional load of (5pF
).
ns
ns
μ
s
ns
ns
t21A(1)
10
10
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相關(guān)代理商/技術(shù)參數(shù) |
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| DDC118IRTCR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC118IRTCRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC118IRTCT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:IC ADC 20BIT OCTAL 48-VQFN |
| DDC118IRTCT | 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC ((NW)) |
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