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參數(shù)資料
| 型號： | DM560P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set |
| 中文描述： | .90綜合數(shù)據(jù)/傳真/語音/揚聲器調(diào)制解調(diào)器設備集 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 242K |
| 代理商： | DM560P |
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DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Preliminary
Version: DM560P-DS-P07
August 11, 2000
13
FIFO Control Register (FCR): Address 2
Reset State 00h , write only
bit7
bit6
RCVR
Trig
(MSB)
(LSB)
bit5 bit4 bit3
0
0
bit2
TxFIFO
Reset
bit1
RxFIFO
Reset
bit0
FIFO
Enable
RCVR
Trig
DMA
Mode
This is a write only register at the same location as
the IIR, which is a read only register. This register is
used to enable the FIFOs, clear the FIFOs, set the
RxFIFO trigger level, and select the type of DMA
signal.
Bit 0: FIFO Enable, This bit is always high
Bit 1: Writing a 1 to FCR1 clears all bytes in the
RxFIFO and resets the counter logic to 0.
Bit 2: Writing a 1 to FCR2 clears all bytes in the
TxFIFO and resets the counter logic to 0.
Bit 3: Setting FCR3 to 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1
if FCR0 = 1.
Bit 4-5: Reserved
Bit 6-7: FCR6, FCR7 are used to set the trigger level
for the RxFIFO interrupt.
FCR6
0
0
1
FCR7
0
1
0
RxFIFO Trigger Level
01
04
08
Line Control Register (LCR): Address 3
Reset State 00h, Write Only
bit7
bit6
DLAB SBRK STP EPS PEN STB WLS1 WLS0
bit5 bit4 bit3 bit2
bit1
bit0
This register is available to maintain compatibility
with the standard 16550 register set, and provides
information to the internal hardware that is used to
determine the number of bits per character.
WLS1
0
0
1
1
WLS0
0
1
0
1
Word Length
5 bits
6 bits
7 bits
8 bits
Bit 0-1: WLS0-1 specifies the number of bits in each
transmitted and received serial character.
Bit 2: STB specifies the number of stop bits in each
transmitted character. If bit 2 is a logic 0, one
stop bit is generated in the transmitted data. If
bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, one and a half stops
are generated. If bit 2 is a logic 1 when either a
6-, 7- or 8-bit word length is selected, two stop
bits are generated. The Receiver checks the
first Stop-bit only, regardless of the number of
Stop bits selected.
Bit 3: Logic 1 indicates that the PC has enabled
parity generation and checking.
Bit 4: Logic 1 indicates that the PC is requesting an
even number of logic 1s (even parity
generation) to be transmitted or checked.
Logic 0 indicates that the PC is requesting odd
parity generation and checking.
Bit 5: When bits 3, 4 and 5 are logic 1, the parity bit
is transmitted and checked by the receiver as
logic 0. If bits 3 and 5 are 1 and bit 4 is logic 0,
then the parity is transmitted and checked as
logic 1.
Bit 6: This is a Break Control bit. When it is set to
logic 1, a break condition is indicated.
Bit 7: The Divisor Latch Access bit must be set to
logic 1 to access the Divisor Latches of the
baud generator during a read or write
operation. It must be set to logic 0 to access
the Receiver Buffer, the Transmitter Holding
Register, or the Interrupt Enable Register.
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