參數(shù)資料
型號(hào)： DM560P
廠商： Electronic Theatre Controls, Inc.
英文描述： V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
中文描述： .90綜合數(shù)據(jù)/傳真/語音/揚(yáng)聲器調(diào)制解調(diào)器設(shè)備集
文件頁數(shù)： 15/43頁
文件大小： 242K
代理商： DM560P
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Modem Status Register (MSR): Address 6
Preliminary
Version: DM560P-DS-P07
August 11, 2000
15
Reset State bit 0-3 : low , bit 4-7: Input Signal
bit7
bit6 bit5
bit4 bit3
DCD RI
DSR CTS DDCD TERI DDSR DCTS
bit2
bit1
bit0
This 8-bit register provides the current state of the
control lines from the Modem to the CPU. In addition,
four bits of the Modem Status Register provide change
information. These bits are set to a logic 1 whenever a
control input from the Modem changes state. They are
reset to logic 0 whenever the CPU reads the Modem
Status Register.
Bit 0: This bit is the Delta Clear to Send (DCTS)
indicator. Bit 0 indicates that the CTS (MSR Bit 4) has
changed state since the last time it was read by the
CPU.
Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR (MSR Bit 5) has
changed state since the last time it was read by the
CPU.
Bit 2: This bit is the Trailing Edge of Ring indicator. Bit
2 indicates that the RI (MSR Bit 6) has changed from a
low to a high state.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD)
indicator. Bit 3 indicates that the DCD (MSR Bti 7) has
changed state.
Note: Whenever bit 0, 1, 2 or 3 is set to a logic 1, a
Modem Status Interrupt is generated.
Bit 4: This bit reflects the value of MSR Bit 4 (CTS).
Bit 5: This bit reflects the value of MSR Bit 5 (DSR).
Bit 6: This bit reflects the value of MSR Bit 6 (RI).
Bit 7: This bit reflects the value of MSR Bit 7 (DCD).
Scratch Register (SCR): Address 7
Reset State 00h
This 8-bit Read/Write Register does not control the
UART in any way. It is intended as a Scratch Pad
Register to be used by the programmer to hold data
temporarily.
Divisor Latch (DLL): Address 0 (DLAB = 1)
Reset State 00h
bit7
bit6
bit5
bit4
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
bit3
bit2
bit1
bit0
This register contains baud rate information from the
host PC. The PC sets the Divisor Latch Register
values.
Divisor Latch (DLM): Address 1 (DLAB = 1)
Reset State 00h
bit7
bit6
bit5
bit4
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
bit3
bit2
bit1
bit0
This register contains baud rate information from the
host PC.
Note: Two 8-bit latches (DLL-DLM) store the divisor in
16-digit binary format. The desired baud rate can be
obtained by dividing the 115200Hz clock by the
divisor.
Desired
Baud Rate
50
75
110
150
300
600
1200
2400
4800
9600
19200
38400
57600
115200
Divisor
Value
2304
1536
1047
768
384
192
96
48
24
12
6
3
2
1
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