參數(shù)資料
型號(hào)： DM560P
廠商： Electronic Theatre Controls, Inc.
英文描述： V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
中文描述： .90綜合數(shù)據(jù)/傳真/語(yǔ)音/揚(yáng)聲器調(diào)制解調(diào)器設(shè)備集
文件頁(yè)數(shù)： 29/43頁(yè)
文件大?。?/td> 242K
代理商： DM560P
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6581/82 Pin Description
(continued)
Pin No.
Pin Name
I/O
69
/RESET
I
Reset Pin Of DSP Chip
, low active.
73
/IRQ0
I
Interrupt 0 Input
74
/IRQ1
I
Interrupt 1 Input
75
/IRQ2
I
Interrupt 2 Input
76
/IRQ3
I
Interrupt 3 Input
91, 92, 93
TEST, TEST1,
TEST2
DM6582 as followed:
When Test=0
Test1 0,PLL output clock is 80.64 MHZ.
1,PLL output clock is 89.74 MHZ.
When Test=1:
Reserved for mass production testing mode.
All these 3 pins are pulled low internally.
96
FR_SP1
I/O
Frame Signal Of Serial Port 1
97
TD_SP1
O
Data Output Pin Of Serial Port 1
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP1 signal.
98
RD_SP1
I
Data Input Pin Of The Serial Port 1
The serial data is sampled at the falling edge of the SCLK. The MSB is
coming immediately after the falling of FR_SP1 signal.
99
SCLK
I
Reference Clock For Serial Port 1 And Serial Port 2
100
TD_SP2
O
Data Output Pin Of Serial Port 2
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP2 signal.
Preliminary
Version: DM560P-DS-P07
August 11, 2000
29
Description
I
These three pins define the testing mode operation of DM6581/
DM6581/82 Functional Description
System Clock
Reference Oscillator Clock
The reference frequency is provided by an external
40.32 MHz crystal oscillator. This is the clock source
of the Data Pump.
DSP Clock
This DSP clock is the output of an internal PLL
frequency synthesizer and its frequency can be
selected by Test1 pin. (see pin description )
CODEC Clock
This clock is output via the CODEC_CLK Pin as the
reference clock of the codec chip. This clock is derived
from dividing reference oscillator clock by two.
Serial Port
There are two serial ports to provide the interface with
CODEC chip. The serial port 1 (SP1) transfers 32 bits
in each frame while the serial port 2 can transfer 64
bits in each frame. The frame signal of each serial port
can be configured as either input signal or output
signal by the Serial Port Control Register (SPC).
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