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參數(shù)資料
| 型號： | DM9331A |
| 文件頁數(shù)： | 19/43頁 |
| 文件大小： | 509K |
| 代理商： | DM9331A |
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DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Preliminary 19
Version: DM9331-DS-P02
September 21, 2001
Basic Mode Control Register (BMCR) -
00
Bit
0.15
Bit Name
Reset
Default
0, RW/SC
Description
Reset:
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
Loopback:
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MCI receive outputs
Speed select:
1 = 100Mbps
0 = invalid
Auto-negotiation enable:
1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-
negotiation status.
Power Down:
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MCI.
1=Power down
0=Normal operation
Isolate:
1 = Isolates the DM9331 from the MCI with the exception of the
serial management. (When this bit is asserted, the DM9331 does
not respond to the TXD[0:1] and TXEN inputs, and it shall present a
high impedance on its TXCLK, RXDV, and RXD[0:1] outputs. When
the PHY is isolated from the MCI, it shall respond to the
management transactions)
0 = Normal operation
Restart auto-negotiation:
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning a value of 1 until auto-
negotiation is initiated by the DM9331. The operation of the auto-
negotiation process will not be affected by the management entity
that clears this bit
0 = Normal operation
Duplex mode:
1 = Full duplex operation. Duplex selection is allowed when Auto-
negotiation is disabled (bit 12 of this register is cleared). With auto-
negotiation enabled, this bit reflects the duplex capability selected by
auto-negotiation
0 = Normal operation
0.14
Loopback
0, RW
0.13
Speed selection
1, RW
0.12
Auto-negotiation
enable
1, RW
0.11
Power down
0, RW
0.10
Isolate
0,RW
0.9
Restart auto-
negotiation
0,RW/SC
0.8
Duplex mode
1,RW
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相關(guān)代理商/技術(shù)參數(shù) |
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| DM9331AE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip |
| DM9332 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
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| DM9334 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-Bit Addressable Latch |
| DM9334 WAF | 制造商:Texas Instruments 功能描述: |
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