參數(shù)資料
型號: DM9331A
文件頁數(shù): 21/43頁
文件大?。?/td> 509K
代理商: DM9331A
DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
Preliminary 21
Version: DM9331-DS-P02
September 21, 2001
Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9331 device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
4.15
Bit Name
NP
Default
0,RO/P
Description
Next page indication:
0 = No next page available
1 = Next page available
The DM9331 has no next page, so this bit is permanently set to 0
Acknowledge:
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9331's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
Remote fault:
1 = Local device senses a fault condition
0 = No fault detected
Reserved:
Write as 0, ignore on read
Flow control support:
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 support:
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9331 does not support 100BASE-T4 so this bit is
permanently set to 0
100BASE-TX full duplex support:
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX support:
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
Reserved
Reserved
<00001>, RW
Protocol selection bits:
These bits contain the binary encoded protocol selector supported
by this node.
<00001> indicates that this device supports IEEE 802.3 CSMA/CD.
4.14
ACK
0,RO
4.13
RF
0, RW
4.12-4.11
Reserved
0, RW
4.10
FCS
0, RW
4.9
T4
0, RO/P
4.8
TX_FDX
1, RW
4.7
TX_HDX
1, RW
4.6
4.5
Reserved
Reserved
Selector
0, RW
0, RW
4.4-4.0
Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
5.15
Bit Name
NP
Default
0, RO
Description
Next page indication:
0 = Link partner, no next page available
1 = Link partner, next page available
Acknowledge:
1 = Link partner ability data reception acknowledged
5.14
ACK
0, RO
相關PDF資料
PDF描述
DM9338
DM9334 8-Bit Addressable Latch
DM9334N 8-Bit Addressable Latch
DM9348
DM93L00
相關代理商/技術參數(shù)
參數(shù)描述
DM9331AE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
DM9332 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
DM9332EP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
DM9334 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-Bit Addressable Latch
DM9334 WAF 制造商:Texas Instruments 功能描述: