參數(shù)資料
型號(hào): DP83848CVVX/NOPB
廠商: National Semiconductor
文件頁(yè)數(shù): 31/86頁(yè)
文件大小: 0K
描述: TXRX ETHERNET PHYTER 48LQFP
產(chǎn)品培訓(xùn)模塊: PHYTER® Family
標(biāo)準(zhǔn)包裝: 1
系列: *
其它名稱: DP83848CVVX/NOPBDKR
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5.5.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All
interrupt sources are disabled by default. Setting bit 1
(INTEN) of MICR (0x11h) will enable interrupts to be out-
put, dependent on the interrupt mask set in the lower byte
of the MISR (0x12h). The PWR_DOWN/INT pin is asyn-
chronously asserted low when an interrupt condition
occurs. The source of the interrupt can be determined by
reading the upper byte of the MISR. One or more bits in the
MISR will be set, denoting all currently pending interrupts.
Reading of the MISR clears ALL pending interrupts.
Example: To generate an interrupt on a change of link sta-
tus or on a change of energy detect power state, the steps
would be:
— Write 0003h to MICR to set INTEN and INT_OE
— Write 0060h to MISR to set ED_INT_EN and
LINK_INT_EN
— Monitor PWR_DOWN/INT pin
When PWR_DOWN/INT pin asserts low, user would read
the MISR register to see if the ED_INT or LINK_INT bits
are set, i.e. which source caused the interrupt. After read-
ing the MISR, the interrupt bits should clear and the
PWR_DOWN/INT pin will deassert.
5.6 Energy Detect Mode
When Energy Detect is enabled and there is no activity on
the cable, the DP83848C will remain in a low power mode
while monitoring the transmission line. Activity on the line
will cause the DP83848C to go through a normal power up
sequence. Regardless of cable activity, the DP83848C will
occasionally wake up the transmitter to put ED pulses on
the line, but will otherwise draw as little power as possible.
Energy detect functionality is controlled via register Energy
Detect Control (EDCR), address 0x1Dh.
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