參數(shù)資料
型號(hào)： DP83848CVVX/NOPB
廠商： National Semiconductor
文件頁數(shù)： 6/86頁
文件大?。?/td> 0K
描述： TXRX ETHERNET PHYTER 48LQFP
產(chǎn)品培訓(xùn)模塊： PHYTER® Family
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： DP83848CVVX/NOPBDKR
13
www.national.com
DP
83
84
8
C
AN_EN (LED_ACT/COL)
AN_1 (LED_SPEED)
AN_0 (LED_LINK)
S, O, PU
26
27
28
Auto-Negotiation Enable: When high, this enables Auto-Negoti-
ation with the capability set by ANO and AN1 pins. When low, this
puts the part into Forced Mode with the capability set by AN0 and
AN1 pins.
AN0 / AN1: These input pins control the forced or advertised op-
erating mode of the DP83848C according to the following table.
The value on these pins is set by connecting the input pins to
GND (0) or VCC (1) through 2.2 k resistors. These pins should
NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848C at Hard-
ware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
MII_MODE (RX_DV)
SNI_MODE (TXD_3)
S, O, PD
39
6
MII MODE SELECT: This strapping option pair determines the
operating mode of the MAC Data Interface. Default operation (No
pull-ups) will enable normal MII Mode of operation. Strapping
MII_MODE high will cause the device to be in RMII or SNI mode
of operation, determined by the status of the SNI_MODE strap.
Since the pins include internal pull-downs, the default values are
0.
The following table details the configurations:
LED_CFG (CRS)
S, O, PU
40
LED CONFIGURATION: This strapping option determines the
mode of operation of the LED pins. Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the strap option. All modes are con-
figurable via register access.
SeeTable 3 for LED Mode Selection.
MDIX_EN (RX_ER)
S, O, PU
41
MDIX ENABLE: Default is to enable MDIX. This strapping option
disables Auto-MDIX. An external pull-down will disable Auto-
MDIX mode.
Signal Name
Type
Pin #
Description
AN_EN AN1
AN0
Forced Mode
0
10BASE-T, Half-Duplex
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-TX, Half-Duplex
0
1
100BASE-TX, Full-Duplex
AN_EN AN1
AN0
Advertised Mode
1
0
10BASE-T, Half/Full-Duplex
1
0
1
100BASE-TX, Half/Full-Duplex
1
0
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1
10BASE-T, Half/Full-Duplex
100BASE-TX,Half/Full-Duplex
MII_MODE SNI_MODE
MAC Interface
Mode
0
X
MII Mode
1
0
RMII Mode
1
10 Mb SNI Mode
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