參數(shù)資料
型號(hào)： DP84412N
英文描述： DRAM Controller
中文描述： DRAM控制器
文件頁(yè)數(shù)： 22/46頁(yè)
文件大?。?/td> 644K
代理商： DP84412N
6.0 Refresh Modes
(Continued)
6.3 ERROR SCRUBBING DURING REFRESH
The DP8440/41 supports error scrubbing during all RAS
DRAM refreshes. Error scrubbing during refresh is selected
through bits C4–C6 with bit C6 set during programming. Er-
ror scrubbing can not be used with staggered refresh. Error
scrubbing during refresh allows a CAS or group of CASs to
assert during the all RAS refresh as shown in Figure 16.
This allows data to be read from the DRAM array and
passed through an Error Detection And Correction Chip,
EDAC. If the EDAC determines that the data contains a sin-
gle bit error and corrects that error, the refresh cycle can be
extended with the input extend refresh, EXTNDRF, and a
read-modify-write operation can be performed by asserting
WE. It is the responsibility of the designer to ensure that WE
is negated. The DP8440 has a 26-bit internal refresh ad-
dress counter that contains the 12 row, 12 column and 2
bank addresses. The DP8441 has a 28-bit internal refresh
address counter that contains the 13 row, 13 column and 2
bank addresses. These counters are configured as bank,
column, row with the row address as the least significant
bits. The bank counter bits are then used with the program-
ming selection to determine which CAS or group of CASs
will assert during a refresh.
TL/F/11718–42
FIGURE 16. Error Scrubbing during Refresh (Two Refresh Cycles Shown)
22
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DP84412N/A+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DRAM Controller
DP84412N/B+ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DRAM Controller
DP8441VLJ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:DRAM Controller
DP8441VLJ-25 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver
DP8441VLJ-40 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver
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