參數(shù)資料
型號(hào)： DPL4519G
廠商： Electronic Theatre Controls, Inc.
英文描述： Sound Processor for Digital and Analog Surround Systems
中文描述： 聲音處理器的數(shù)字和模擬環(huán)繞聲系統(tǒng)
文件頁(yè)數(shù)： 15/64頁(yè)
文件大?。?/td> 1073K
代理商： DPL4519G
PRELIMINARY DATA SHEET
DPL 4519G
Micronas
15
3.1.3. Description of CONTROL Register
3.1.4. Protocol Description
Write to DSP
Read from DSP
Write to Control
Read from Control
Note:
S =
I
2
C-Bus Start Condition from master
I
2
C-Bus Stop Condition from master
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, light gray) or master (= controller dark gray)
NAK =
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from DPL indicating internal error state
Wait = I
2
C-Clock line is held low, while the DPL is processing the I
2
C command.
This waiting time is max. 1 ms
P =
Table 3–3:
CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL
00 hex
1 : RESET
0 : normal
0
Table 3–4:
CONTROL as a Read Register
(only
DPL 4519G
-versions from A2 on)
Name
Subaddress
Bit[15] (MSB)
Bit[14]
Bits[13:0]
CONTROL
00 hex
Reset status after last reading of CONTROL:
0 : no reset occured
1 : reset occured
Internal hardware status:
0 : no error occured
1 : internal error occured
not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on,
bit[15] of CONTROL
will be set; it must be
read once to be resetted.
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK data-byte-
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
sub-addr ACK addr-byte
high
ACK addr-byte
low
ACK
S
read
device
address
Wait
ACK data-byte-
high
ACK data-byte
low
NAK
P
S
write
device
address
Wait
ACK
sub-addr ACK data-byte
high
ACK data-byte
low
ACK
P
S
write
device
address
Wait
ACK
00hex
ACK
S
read
device
address
Wait
ACK data-byte-
high
ACK data-byte
low
NAK
P
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