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參數(shù)資料
| 型號(hào)： | DPL4519G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Sound Processor for Digital and Analog Surround Systems |
| 中文描述： | 聲音處理器的數(shù)字和模擬環(huán)繞聲系統(tǒng) |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 1073K |
| 代理商： | DPL4519G |
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DPL 4519G
PRELIMINARY DATA SHEET
34
Micronas
3.4. Programming Tips
This section describes the preferred method for initial-
izing the DPL 4519G. The initialization is grouped into
four sections: analog signal path, input processing for
I
2
S, and output processing. See Fig. 2–1 on page 7 for
a complete signal flow.
SCART Signal Path
1. Select the source for each analog SCART output
with the ACB register.
I
2
S Inputs
1. Select preferred prescale for I
2
S inputs
(set to 0 dB after RESET).
2. Select I2S3 Resorting matrix according to the chan-
nel order of your decoding device (e.g. for
MAS 3528E chose mode 02
hex
)
Output Channels
1. Select the source channel and matrix for each out-
put.
2. Set audio baseband features
3. Select volume for each output.
3.5. Examples of Minimum Initialization Codes
Initialization of the DPL 4519G according to these list-
ings reproduces sound of the selected standard on the
Main output. All numbers are hexadecimal. The exam-
ples have the following structure:
1. Perform an I
2
C controlled reset of the IC.
2. Write MODUS register
3. Set Source Selection for Main channel
(with matrix set to STEREO).
4. Set Volume Main channel to 0 dB.
3.5.1. Micronas Dolby Digital chipset
(with MAS 3528E)
<84 00 80 00>
<84 00 00 00>
<84 10 00 30 00 20>
<84 10 00 40 01 F2>
<84 12 00 36 00 02>
<84 12 00 0B 07 20>
<84 12 00 08 08 20>
<84 12 00 00 73 00>
// Softreset
// MODUS-Register: I2S slave
// I2S-config-Register
// I2S3 Resorting matrix, Mode 2
// Source Sel. I2S_out = I2S3 - L
t
/R
t
// Source Sel. Main_out = I2S3 - L/R
// Main Volume 0 dB
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