參數(shù)資料
型號(hào)： DPL4519G
廠商： Electronic Theatre Controls, Inc.
英文描述： Sound Processor for Digital and Analog Surround Systems
中文描述： 聲音處理器的數(shù)字和模擬環(huán)繞聲系統(tǒng)
文件頁(yè)數(shù)： 40/64頁(yè)
文件大小： 1073K
代理商： DPL4519G
DPL 4519G
PRELIMINARY DATA SHEET
40
Micronas
4.3. Pin Descriptions
Pin numbers refer to the 80-pin PQFP package
Pin 1,
NC
– Pin not connected.
Pin 2,
I2C_CL
– I
2
C Clock Input/Output (Fig. 4–8)
Via this pin, the I
2
C-bus clock signal has to be sup-
plied. The signal can be pulled down by the DPL in
case of wait conditions.
Pin 3,
I2C_DA
– I
2
C Data Input/Output (Fig. 4–8)
Via this pin, the I
2
C-bus data is written to or read from
the DPL.
Pin 4,
I2S_CL
– I
2
S Clock Input/Output (Fig. 4–11)
Clock line for the I
2
S bus. In master mode, this line is
driven by the DPL; in slave mode, an external I
2
S clock
has to be supplied.
Pin 5,
I2S_WS
– I
2
S Word Strobe Input/Output
(Fig. 4–11)
Word strobe line for the I
2
S bus. In master mode, this
line is driven by the DPL; in slave mode, an external
I
2
S word strobe has to be supplied.
Pin 6,
I2S_DA_OUT1
– I
2
S Data Output (Fig. 4–7)
Output of digital serial sound data of the DPL on the
I
2
S bus.
Pin 7,
I2S_DA_IN1
– I
2
S Data Input 1 (Fig. 4–9)
First input of digital serial sound data to the DPL via
the I
2
S bus.
Pin 8, 9, 10,
TP
– Test pins
Pins 11, 12, 13,
DVSUP*
– Digital Supply Voltage
Power supply for the digital circuitry of the DPL. Must
be connected to a power supply.
Pins 14, 15, 16,
DVSS*
– Digital Ground
Ground connection for the digital circuitry of the DPL.
Pin 17,
I2S_DA_IN2
– I
2
S Data Input 2 (Fig. 4–9)
Second input of digital serial sound data to the DPL via
the I
2
S bus. In all packages except PQFP-80-pin this
pin is also connected to the asynchronous I
2
S inter-
face 3.
Pins 18,
NC
– Pin not connected.
Pins 19,
I2S_CL3
– I
2
S Clock Input (Fig. 4–9)
Clock line for the I
2
S bus. Since only a slave mode is
available an external I
2
S clock has to be supplied.
Pins 20,
I2S_WS3
– I
2
S Word Strobe Input (Fig. 4–9)
Word strobe line for the I
2
S bus. Since only a slave
mode is available an external I
2
S word strobe has to
be supplied.
Pin 21,
RESETQ
– Reset Input (Fig. 4–9)
In the steady state, high level is required. A low level
resets the DPL 4519G.
Pin 22,
I2S_DA_IN3
– I
2
S Data Input 3 (Fig. 4–9)
Asynchronous input of digital serial sound data to the
DPL via the I
2
S bus.
Pins 23,
NC
– Pin not connected.
Pins 24, 25,
DACA_R/L
– Aux Outputs (Fig. 4–16)
Output of the aux signal. A 1 nF capacitor to AHVSS
must be connected to these pins. The DC offset on
these pins depends on the selected aux volume.
Pin 26,
VREF2
– Reference Ground 2
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF2 serves as a
clean ground and should be used as the reference for
analog connections to the Main and AUX outputs.
Pins 27, 28,
DACM_R/L
– Main Outputs
(Fig. 4–16)
Output of the Main signal. A 1 nF capacitor to AHVSS
must be connected to these pins. The DC offset on
these pins depends on the selected Main volume.
Pin 29
NC
– Pin not connected.
Pin 30,
DACM_SUB
– Subwoofer Output (Fig. 4–16)
Output of the subwoofer signal. A 1-nF capacitor to
AHVSS must be connected to this pin. Due to the low
frequency content of the subwoofer output, the value
of the capacitor may be increased for better suppres-
sion of high-frequency noise. The DC offset on this pin
depends on the selected Main volume.
Pins 31, 32
NC
– Pin not connected.
Pins 33, 34,
SC2_OUT_R/L
– SCART2 Outputs
(Fig. 4–18)
Output of the SCART2 signal. Connections to these
pins must use a 100-
series resistor and are intended
to be AC-coupled.
Pin 35,
VREF1
– Reference Ground 1
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF1 serves as a
clean ground and should be used as the reference for
analog connections to the SCART outputs.
Pins 36, 37,
SC1_OUT_R/L
– SCART1 Outputs
(Fig. 4–18)
Output of the SCART1 signal. Connections to these
pins must use a 100-
series resistor and are intended
to be AC-coupled.
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