參數(shù)資料
型號： DPL4519G
廠商： Electronic Theatre Controls, Inc.
英文描述： Sound Processor for Digital and Analog Surround Systems
中文描述： 聲音處理器的數(shù)字和模擬環(huán)繞聲系統(tǒng)
文件頁數(shù)： 41/64頁
文件大小： 1073K
代理商： DPL4519G
PRELIMINARY DATA SHEET
DPL 4519G
Micronas
41
Pin 38,
CAPL_A
– Volume Capacitor Aux (Fig. 4–13)
A 10-
μ
F capacitor to AHVSUP must be connected to
this pin. It serves as a smoothing filter for volume
changes in order to suppress audible plops. The value
of the capacitor can be lowered to 1-
μ
F if faster
response is required. The area encircled by the trace
lines should be minimized; keep traces as short as
possible. This input is sensitive for magnetic induction.
Pin 39,
AHVSUP*
– Analog Power Supply High Volt-
age
Power is supplied via this pin for the analog circuitry of
the DPL. This pin must be connected to the
+
8 V sup-
ply. (+5 V-operation is possible with restrictions in per-
formance)
Pin 40,
CAPL_M
– Volume Capacitor Loudspeakers
(Fig. 4–13)
A 10-
μ
F capacitor to AHVSUP must be connected to
this pin. It serves as a smoothing filter for volume
changes in order to suppress audible plops. The value
of the capacitor can be lowered to 1
μ
F if faster
response is required. The area encircled by the trace
lines should be minimized; keep traces as short as
possible. This input is sensitive for magnetic induction.
Pins 41, 42,
NC
– Pins not connected.
Pins 43, 44,
AHVSS*
– Ground for Analog Power Sup-
ply High Voltage
Ground connection for the analog circuitry of the DPL.
Pin 45,
AGNDC
– Internal Analog Reference Voltage
This pin serves as the internal ground connection for
the analog circuitry. It must be connected to the VREF
pins with a 3.3-
μ
F and a 100-nF capacitor in parallel.
This pins shows a DC level of typically 3.73 V.
Pin 46,
NC
– Pin not connected.
Pins 47, 48,
SC4_IN_L/R
– SCART4 Inputs
(Fig. 4–15)
The analog input signal for SCART4 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 49,
ASG*
– Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pins 50, 51,
SC3_IN_L/R
– SCART3 Inputs
(Fig. 4–15)
The analog input signal for SCART3 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 52,
ASG*
– Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pins 53, 54
SC2_IN_L/R
– SCART2 Inputs (Fig. 4–15)
The analog input signal for SCART2 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 55,
ASG*
– Analog Shield Ground
Analog ground (AHVSS) should be connected to this
pin to reduce cross-coupling between SCART inputs.
Pins 56, 57
SC1_IN_L/R
– SCART1 Inputs (Fig. 4–15)
The analog input signal for SCART1 is fed to this pin.
Analog input connection must be AC-coupled.
Pin 58,
NC
– Pin not connected
Pin 59,
NC
– Pin not connected.
Pin 60
MONO_IN
– Mono Input (Fig. 4–15)
The analog mono input signal is fed to this pin AC-cou-
pled.
Pins 61, 62,
AVSS*
– Analog Power Supply Voltage
Ground connection for the analog IF input circuitry of
the DPL.
Pins 63, 64,
NC
– Pins not connected.
Pins 65, 66,
AVSUP*
– Analog Power Supply Voltage
Power is supplied via this pin for the analog IF input cir-
cuitry of the DPL. This pin must be connected to the
+
5 V supply.
Pin 67, 68, 69,
NC
– Pin not connected.
Pin 70,
TESTEN
– Test Enable Pin (Fig. 4–9)
This pin enables factory test modes. For normal opera-
tion, it must be connected to ground.
Pins 71, 72
XTAL_IN, XTAL_OUT
– Crystal Input and
Output Pins (Fig. 4–12)
These pins are connected to an 18.432 MHz crystal
oscillator which is digitally tuned by integrated capaci-
tances. An external clock can be fed into XTAL_IN
(leave XTAL_OUT vacant in this case). The audio
clock output signal AUD_CL_OUT is derived from the
oscillator. External capacitors at each crystal pin to
ground (AVSS) are required. It should be verified by
layout, that no supply current for the digital circuitry is
flowing through the ground connection point.
Pin 73,
TP
– This pin is needed for factory tests. For
normal operation, it must be left vacant.
Pin 74,
AUD_CL_OUT
– Audio Clock Output
(Fig. 4–12)
This is the 18.432 MHz main clock output.
Pins 75, 76,
NC
– Pins not connected.
Pins 77, 78,
D_CTR_I/O_1/0
– Digital Control Input/
Output Pins (Fig. 4–11)
General purpose input/output pins.
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