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參數(shù)資料
| 型號： | DS1265W |
| 英文描述： | 3.3V 8Mb Nonvolatile SRAM |
| 中文描述： | 3.3V、8Mb非易失SRAM |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 155K |
| 代理商： | DS1265W |
DS1265W
6 of 8
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(T
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
Slew from V
TP
to 0V
t
F
V
CC
Slew from 0V to V
TP
t
R
t
PU
V
CC
Valid to End of Write Protection
t
REC
MIN
TYP
MAX
1.5
UNITS
NOTES
11
s
150
150
s
s
V
CC
Valid to
CE
and
WE
Inactive
2
ms
125
ms
(T
A
= 25 C)
PARAMETER
SYMBOL
Expected Data-Retention Time
t
DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a read cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3.
t
WP
is specified as the logical AND of
CE
or
WE
. t
WP
is measured from the latter of
CE
or
WE
going
low to the earlier of
CE
or
WE
going high.
4.
t
DS
is measured from the earlier of
CE
or
WE
going high.
5.
These parameters are sampled with a 5pF load and are not 100% tested.
6.
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in a high-impedance state during this period.
8.
If
WE
is low or the
WE
low transition occurs prior to, or simultaneously with, the
CE
the output buffers remain in a high-impedance state during this period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1265W-100 | 3.3V 8Mb Nonvolatile SRAM |
| DS1265W-100-IND | 3.3V 8Mb Nonvolatile SRAM |
| DS1265W-150 | 3.3V 8Mb Nonvolatile SRAM |
| DS1265W-150-IND | 3.3V 8Mb Nonvolatile SRAM |
| DS1275N | Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1265W-100 | 功能描述:NVRAM 3.3V 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1265W-100+ | 功能描述:NVRAM 3.3V 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1265W-100IND | 功能描述:NVRAM 3.3V 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1265W-100-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V 8Mb Nonvolatile SRAM |
| DS1265W-100IND+ | 功能描述:NVRAM 3.3V 8M NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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