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參數(shù)資料
| 型號： | DS1875T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SFP CTRLR/TRIPLEXER 38-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 應用： | 光纖 |
| 接口： | I²C |
| 電源電壓： | 2.85 V ~ 3.9 V |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-TQFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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DS1875
PON Triplexer and SFP Controller
18
______________________________________________________________________________________
BIAS and MOD Output as a Function of
Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal oper-
ation, the outputs are disabled within tOFF. When TX-D
is deasserted (logic 0), the DS1875 turns on the MOD
output with the value associated with the present tem-
perature and initializes the BIAS using the same search
algorithm used at startup. When asserted, the SOFT
TX-D bit (Lower Memory, Register 6Eh) offers a soft-
ware control identical to the TX-D pin (see Figure 2).
APC and Quick-Trip Shared Comparator
Timing
As shown in Figure 3, the DS1875’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP HI, TXP LO, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Six of every eight comparator readings are used for
APC loop-bias current control. The other two updates
are used to check the HTXP/LTXP (monitor diode volt-
age) and the HBIAS (MON1) signals against the inter-
nal APC and BIAS reference. If the last APC
comparison was higher than the APC set point, it
makes an HTXP comparison, and if it is lower, it makes
an LTXP comparison. Depending on the results of the
comparison, the corresponding alarms and warnings
(TXP HI, TXP LO) are asserted or deasserted.
The DS1875 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options suitable for
burst-mode transmitters. The rising edge of BEN trig-
gers the sample to occur, and the Update Rate register
(Table 02h, Register 88h) determines the sampling time.
The first sample occurs (tFIRST) after the rising edge of
BEN. The internal clock is asynchronous to BEN, caus-
ing a ±50ns uncertainty regarding when the first sample
will occur following BEN. After the first sample occurs,
subsequent samples occur on a regular interval, tREP.
Table 2 shows the sample rate options available.
Updates to the TXP HI and TXP LO quick-trip alarms do
not occur during the BEN low time. The BIAS HI quick
trip can be sampled during the burst-low time. Any
*
All codes greater than 1001b (1010b to 1111b) use the
maximum sample time of code 1001b.
BEN
APC QUICK-TRIP
SAMPLE TIMES
HBIAS
SAMPLE
tFIRST
tREP
HTXP/LTXP
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
Figure 3. APC Loop and Quick-Trip Sample Timing
Table 2. Update Rate Timing
APC_SR[3:0]
MINIMUM TIME
FROM BEN TO
FIRST SAMPLE
(tFIRST) ±50ns
(ns)
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SAMPLE (tREP)
(ns)
0000b
350
800
0001b
550
1200
0010b
750
1600
0011b
950
2000
0100b
1350
2800
0101b
1550
3200
0110b
1750
3600
0111b
2150
4400
1000b
2950
6000
1001b*
3150
6400
TX-D
IBIAS
VMOD
tOFF
tON
tOFF
Figure 2. TX-D Timing
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