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參數(shù)資料
| 型號(hào)： | DS1875T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SFP CTRLR/TRIPLEXER 38-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 光纖 |
| 接口： | I²C |
| 電源電壓： | 2.85 V ~ 3.9 V |
| 封裝/外殼： | 38-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 38-TQFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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DS1875
PON Triplexer and SFP Controller
22
______________________________________________________________________________________
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the ADC alarms and the QT alarms to select
which comparisons cause it to assert. Unlike TX-F, the
FETG output is always latched. Its output polarity is
programmable to allow an external nMOS or pMOS to
open during alarms to shut off the laser-diode current.
If the FETG output triggers, indicating that the DS1875
is in shutdown, it requires TX-D, SOFT TX-D, or cycling
power to be reset. Under all conditions, when the ana-
log outputs are reinitialized after being disabled, all the
alarms with the exception of the VCC low ADC alarm
are cleared. The VCC low alarm must remain active to
prevent the output from attempting to operate when
inadequate VCC exists to operate the laser driver. Once
adequate VCC is present to clear the VCC low alarm,
the outputs are enabled following the same sequence
as the power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOS or
pMOS. This requires that the FETG output can sink or
source current. Because the DS1875 does not know if it
should sink or source current before VCC exceeds
VPOA, which triggers the EE recall, this output is high
impedance when VCC is below VPOA (see the Low-
Voltage Operation section for details and diagram). The
application circuit should use a pullup or pulldown
resistor on this pin that pulls FETG to the alarm/shut-
down state (high for a pMOS, low for a nMOS). Once
VCC is above VPOA, the DS1875 pulls the FETG output
to the state determined by the FETG DIR bit (Table 02h,
Register 89h). Set FETG DIR to 0 if an nMOS is used
and 1 if a pMOS is used.
Determining Alarm Causes Using the I2C
Interface
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1875’s alarm trap bytes
(ATB) through the I2C interface (Table 01h, Registers
F8h–FBh). The ATB has a bit for each alarm. Any time an
alarm occurs, regardless of the mask bit’s state, the
DS1875 sets the corresponding bit in the ATB. Active ATB
bits remain set until written to 0s through the I2C interface.
On power-up, the ATB is 0s until alarms dictate otherwise.
FETG causes additional alarms that make it difficult to
determine the root cause of the problem. Therefore, no
updates are made to the ATB when FETG occurs.
IBIAS
VMOD
DETECTION OF
FETG FAULT
tOFF
tON
tOFF
TX-D
tFETG:ON
FETG*
*FETG DIR = 0
tFETG:OFF
Figure 8. FETG/Output Disable Timing (Fault Condition Detected)
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
VCC >
VPOA
TX-D
NONMASKED
FETG ALARM
FETG
MOD AND
BIAS
OUTPUTS
Yes
0
FETG
DIR
Enabled
Yes
0
1
FETG
DIR
Disabled
Yes
1
X
FETG
DIR
Disabled
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| DS1876T+ | 功能描述:ADC / DAC多通道 SFP+ Controller w/ Dual LDD Interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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