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參數(shù)資料
| 型號： | DS1875T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SFP CTRLR/TRIPLEXER 38-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 應用： | 光纖 |
| 接口： | I²C |
| 電源電壓： | 2.85 V ~ 3.9 V |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 38-TQFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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DS1875
Die Identification
The DS1875 has an ID hard-coded to its die. Two regis-
ters (Table 02h, Registers 86h–87h) are assigned for
this feature. Byte 86h reads 75h to identify the part as
the DS1875; byte 87h reads the die revision.
Low-Voltage Operation
The DS1875 contains two power-on reset (POR) levels.
The lower level is a digital POR (VPOD) and the higher
level is an analog POR (VPOA). At startup, before the
supply voltage rises above VPOA, the outputs are dis-
abled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM (SEE)), and all analog circuitry is
disabled. When VCC reaches VPOA, the SEE is
recalled, and the analog circuitry is enabled. While VCC
remains above VPOA, the device is in its normal operat-
ing state, and it responds based on its nonvolatile con-
figuration. If during operation VCC falls below VPOA but
is still above VPOD, the SRAM retains the SEE settings
from the first SEE recall, but the device analog is shut
down and the outputs are disabled. FETG is driven to
its alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above VPOA, the device immediately resumes normal
functioning. When the supply voltage falls below VPOD,
the device SRAM is placed in its default state and
another SEE recall is required to reload the nonvolatile
settings. The EEPROM recall occurs the next time VCC
exceeds VPOA. Figure 9 shows the sequence of events
as the voltage varies.
Any time VCC is above VPOD, the I2C interface can be
used to determine if VCC is below the VPOA level. This
is accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCC is below VPOA. When VCC rises above VPOA,
RDYB is timed (within 500s) to go to 0, at which point
the part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds VPOA, allowing the device address
to be recalled from the EEPROM.
Enhanced RSSI Monitoring (Dual Range
Functionality)
The DS1875 offers a new feature to improve the accu-
racy and range of MON3, which is most commonly
used for monitoring RSSI. This feature enables right-
shifting (along with its gain and offset settings) when
the input signal is below a set threshold (within the
range that benefits using right-shifting) and then auto-
matically disables right-shifting (recalling different gain
and offset settings) when the input signal exceeds the
threshold. Also, to prevent “chattering,” hysteresis pre-
vents excessive switching between modes in addition
to ensuring that continuity is maintained. Dual range
operation is enabled by default (factory programmed in
EEPROM). However, it can easily be disabled through
the RSSI_FF and RSSI_FC bits. When dual range oper-
ation is disabled, MON3 operates identically to the
other MON channels, although featuring a differential
input.
VCC
VPOA
VPOD
FETG
SEE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED
TO 0
RECALLED
VALUE
RECALLED
VALUE
DRIVEN TO
FETG DIR
NORMAL
OPERATION
DRIVEN TO
FETG DIR
SEE RECALL
Figure 9. SEE Timing
PON Triplexer and SFP Controller
______________________________________________________________________________________
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