參數(shù)資料
型號(hào)： DS1875T+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 14/92頁(yè)
文件大小： 0K
描述： IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： 光纖
接口： I²C
電源電壓： 2.85 V ~ 3.9 V
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-TQFN（5x7）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
DS1875
Right-Shifting ADC Result
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale value defined by a
standard’s specification, then right-shifting can be used
to adjust the predetermined full-scale analog measure-
ment range while maintaining the weighting of the ADC
results. The DS1875’s range is wide enough to cover all
requirements; when the maximum input value is
≤ 1/2
the FS value, right-shifting can be used to obtain
greater accuracy. For instance, the maximum voltage
might be 1/8th the specified predetermined full-scale
value, so only 1/8th the converter’s range is used. An
alternative is to calibrate the ADC’s full-scale range to
1/8th the readable predetermined full-scale value and
use a right-shift value of 3. With this implementation, the
resolution of the measurement is increased by a factor
of 8, and because the result is digitally divided by 8 by
right-shifting, the bit weight of the measurement still
meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of RIGHT SHIFT1/0 registers
(Table 02h, Registers 8Eh–8Fh). Four analog channels,
MON1–MON4, have 3 bits each allocated to set the
number of right-shifts. Up to seven right-shift operations
are allowed and are executed as a part of every con-
version before the results are compared to the high and
low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
62h–6Bh). This is true during the setup of internal cali-
bration as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the ADC
alarms and the QT alarms to select which comparisons
cause it to assert. In addition, the FETG alarm is selec-
table through the TX-F mask to cause TX-F to assert. All
alarms, with the exception of FETG, only cause TX-F to
remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, SOFT TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, it indicates
that the DS1875 is in shutdown and requires TX-D,
SOFT TX-D, or cycling power to reset. Only enabled
alarms activate TX-F (see Figure 7). Table 4 shows
TX-F as a function of TX-D and the alarm sources.
Table 4. TX-F as a Function of TX-D and
Alarm Sources
VCC > VPOA
TX-D
NONMASKED
TX-F ALARM
TX-F
No
X
1
Yes
0
Yes
0
1
Yes
1
X
0
TX-F LATCHED OPERATION
TX-F NONLATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
DETECTION OF
TX-F FAULT
TX-F
Figure 7. TX-F Timing
PON Triplexer and SFP Controller
______________________________________________________________________________________
21
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