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參數(shù)資料
型號(hào)： DS1875T+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 89/92頁(yè)
文件大小： 0K
描述： IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： 光纖
接口： I²C
電源電壓： 2.85 V ~ 3.9 V
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-TQFN（5x7）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
DS1875
Note 1:
All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative.
Note 2:
Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. SW, DAC1, and M4DAC are not loaded.
Note 3:
See the
Safety Shutdown (FETG) Output section for details.
Note 4:
Eight ranges allow the full scale to change from 625mV to 2.5V.
Note 5:
Eight ranges allow the full scale to change from 312.5mV to 1.25V.
Note 6:
This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register
description for available full-scale ranges.
Note 7:
The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56k
Ω.
Note 8:
This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register
description for available full-scale ranges.
Note 9:
The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz.
Note 10: See the
APC and Quick-Trip Shared Comparator Timing section for details.
Note 11: Guaranteed by design.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 13: CB—Total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
I2C TIMING SPECIFICATIONS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 15.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 12)
0
400
kHz
Clock Pulse-Width Low
tLOW
1.3
μs
Clock Pulse-Width High
tHIGH
0.6
μs
Bus-Free Time Between STOP
and START Condition
tBUF
1.3
μs
START Hold Time
tHD:STA
0.6
μs
START Setup Time
tSU:STA
0.6
μs
Data in Hold Time
tHD:DAT
0
0.9
μs
Data in Setup Time
tSU:DAT
100
ns
Capacitive Load for Each Bus Line
CB
400
pF
Rise Time of Both SDA and SCL
Signals
tR
(Note 13)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
(Note 13)
20 +
0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
μs
EEPROM Write Time
tW
(Note 14)
20
ms
PON Triplexer and SFP Controller
_______________________________________________________________________________________
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