參數(shù)資料
型號(hào): DS21352LB
廠商: Maxim Integrated Products
文件頁數(shù): 128/137頁
文件大小: 0K
描述: IC TXRX 1-CHIP T1 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測(cè)器
DS21352/DS21552
90 of 137
16.4 PROTECTED INTERFACES
In certain applications, such as connecting to the PSTN, it is required that the network interface be
protected from and resistant to certain electrical conditions. These conditions are divided into two
categories, surge and power line cross. A typical cause of surge is lightening strike. Power line cross
refers to accidental contact with high voltage power wiring. For protection against surges, additional
components and PCB layout considerations are required to reroute and dissipate this energy. In a surge
event, the network interface must not be damaged and continue to work after the event. In the event of a
power line contact, components such as fuses or PTCs that can “open” the circuit are required to prevent
the possibility of a fire caused by overheating the transformer. The circuit examples in this data sheet are
for “Secondary Over Voltage Protection” schemes for the line terminating equipment. Primary protection
is typically provided by the network service provide and is external to the equipment.
Figure 16-6 shows an example circuit for the 5 volt device and Figure 16-7 is an example for the 3.3
device. In both examples, fuses are used to provide protection against power line cross. 470 ohm input
resistors on the receive pair, a transient suppresser and a diode bridge on the transmit pair provide surge
protection. Resistors R1 – R4 provide surge protection for the fuse. Careful selection of the transformer
will allow the use of a fuse that requires no additional surge protection such as the circuit shown in Figure
16-7. The circuit shown in Figure 16-7 is required for 3.3 volt operation since additional resistance in the
transmit pair cannot be tolerated. For more information on line interface design, consult the T1 Line
Interface Design Criteria (note 353) and Secondary Over Voltage Protection (note 324) application notes.
These notes are available from Dallas Semiconductor’s web site.
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