參數(shù)資料
型號: DS21352LB
廠商: Maxim Integrated Products
文件頁數(shù): 60/137頁
文件大?。?/td> 0K
描述: IC TXRX 1-CHIP T1 3.3V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
29 of 137
8F
R/W
Receive Channel 16
RC16
90
R/W
Receive HDLC DS0 Control Register 1
RDC1
91
R/W
Receive HDLC DS0 Control Register 2
RDC2
92
R/W
Transmit HDLC DS0 Control Register 1
TDC1
93
R/W
Transmit HDLC DS0 Control Register 2
TDC2
94
R/W
Interleave Bus Operation Register
IBO
95
R/W
Test 3 SEE NOTE 1
TEST3 (set to 00h)
96
R/W
Test 4 SEE NOTE 1
TEST4 (set to 00h)
97
-
not present
-
98
-
not present
-
99
-
not present
-
9A
-
not present
-
9B
-
not present
-
9C
-
not present
-
9D
-
not present
-
9E
-
not present
-
9F
-
not present
-
NOTES:
1. TEST1, TEST2, TEST3 and TEST4 registers are used by the factory; these registers must be cleared (set to 00h) on power–
up initialization to insure proper operation.
2. Register banks Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
3. Upper nibble of the PCVCR1 register is used for MOSCR1
6. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21352/552 is configured via a set of eleven control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS21352/552 has been
initialized, the control registers will only need to be accessed when there is a change in the system
configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control
Registers (TCR1 and TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven
registers are described in this section.
6.1 POWER-UP SEQUENCE
On power–up, after the supplies are stable the DS21352/552 should be configured for operation by
writing to all of the internal registers (this includes setting the Test Registers to 00h) since the contents of
the internal registers cannot be predicted on power–up. The LIRST (CCR7.7) should be toggled from
zero to one to reset the line interface circuitry (it will take the DS21352/552 about 40ms to recover from
the LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit
should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled).
6.2 DEVICE ID
There is a device IDentification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a zero indicating that a T1 device is present. The next 3 MSBs are used to indicate which T1
device is present; DS2152, DS21352, or DS21552. The E1 pin–for–pin compatible SCTs will have a
logic one in the MSB position with the following 3 MSBs indicating which E1 SCT is present; DS2154,
DS21354, or DS21554. Table 6-1 represents the possible variations of these bits and the associated SCT.
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
Bit 6
Bit 5
Bit 4
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit.
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