參數(shù)資料
型號: DS21352LB
廠商: Maxim Integrated Products
文件頁數(shù): 52/137頁
文件大?。?/td> 0K
描述: IC TXRX 1-CHIP T1 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補(bǔ)償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
21 of 137
4.1.3 PARALLEL CONTROL PORT PINS
Signal Name:
INT*
Signal Description:
Interrupt
Signal Type:
Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status
Register. Active low, open drain output
Signal Name:
FMS
Signal Description:
Framer Mode Select
Signal Type:
Input
Selects the DS2152 mode when high or the DS21352/552 mode when low. If high, the JTRST is internally pulled low. If low,
JTRST has normal JTAG functionality. This pin has a 10k pull up resistor.
Signal Name:
TEST
Signal Description:
3–State Control
Signal Type:
Input
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when FMS = 0 and JTRST* is
tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST* = 1. Useful for board level testing.
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
AD0 TO AD7
Signal Description:
Data Bus [D0 to D7] or Address/Data Bus
Signal Type:
Input
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8–
bit multiplexed address / data bus.
Signal Name:
A0 TO A6
Signal Description:
Address Bus
Signal Type:
Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins
are not used and should be tied low.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*),
ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis ().
Signal Name:
RD*(DS*)
Signal Description:
Read Input - Data Strobe
Signal Type:
Input
RD* and DS* are active low signals. DS active HIGH when MUX = 0. See bus timing diagrams.
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