參數(shù)資料
型號： DS2152L+
廠商： Maxim Integrated Products
文件頁數(shù)： 3/97頁
文件大?。?/td> 0K
描述： IC TXRX T1 1CHIP ENHNCD 100-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
功能： 單芯片收發(fā)器
接口： T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 管件
包括： DSX-1 和 CSU 線路補償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面： 1429 (CN2011-ZH PDF)
DS2152
11 of 97
2.1 Transmit Side Digital Pins
PIN
NAME
FUNCTION
46
TCLK
Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit
side formatter.
47
TSER
Transmit Serial Data. Transmit NRZ serial data. Sampled on the falling edge of
TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled.
53
TCHCLK
Transmit Channel Clock. A 192kHz clock that pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled.
Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
33
TCHBLK
Transmit Channel Block. A user-programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with TCLK when the transmit side
elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic
store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all T1 channels are used such as Fractional T1, 384kbps (H0),
768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert
applications, for external per-channel loopback, and for per-channel conditioning. See
Section 10 for details.
51
TSYSCLK
Transmit System Clock. 1.544MHz or 2.048MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use
the transmit side elastic store. Can be burst at rates up to 8.192MHz.
34
TLCLK
Transmit Link Clock. 4 kHz or 2kHz (ZBTSI) demand clock for the TLINK input. See
Section 12 for details. Transmit Link Data [TLINK].
35
TLINK
Transmit Link Data. If enabled via TCR1.2, this pin will be sampled on the falling
edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position
(D4) or the Z-bit position (ZBTSI). See Section 12 for details.
37
TSYNC
Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries
for the transmit side. Via TCR2.2, the DS2152 can be programmed to output either a
frame or multiframe pulse at this pin. If this pin is set to output pulses at frame
boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling
frames. See Section 16 for details.
52
TSSYNC
Transmit System Sync. Only used when the transmit side elastic store is enabled. A
pulse at this pin will establish either frame or multiframe boundaries for the transmit
side. Should be tied low in applications that do not use the transmit side elastic store.
48
TSIG
Transmit Signaling Input. When enabled, this input will sample signaling bits for
insertion into outgoing PCM T1 data stream. Sampled on the falling edge of TCLK
when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled.
49
TESO
Transmit Elastic Store Data Output. Updated on the rising edge of TCLK with data
out of the transmit side elastic store whether the elastic store is enabled or not. This pin
is normally tied to TDATA.
50
TDATA
Transmit Data. Sampled on the falling edge of TCLK with data to be clocked through
the transmit side formatter. This pin is normally tied to TESO.
43
TPOSO
Transmit Positive Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. Can be programmed to source NRZ data
via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI.
42
TNEGO
Transmit Negative Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI.
41
TCLKO
Transmit Clock Output. Buffered clock that is used to clock data through the transmit
side formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI.
38
TPOSI
Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data to be
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2152L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2152L-ES 制造商:DALL 功能描述:
DS2152LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2152LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2153DK 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP
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