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參數(shù)資料
| 型號(hào)： | DS2152L+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/97頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1 1CHIP ENHNCD 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 包括： | DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測(cè)器 |
| 產(chǎn)品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS2152
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PIN
NAME
FUNCTION
transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the
LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.
39
TNEGI
Transmit Negative Data Input. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the
LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.
40
TCLKI
Transmit Clock Input. Line interface transmit clock. Can be internally connected to
TCLKO by tying the LIUC pin high.
2.2 Receive Side Digital Pins
PIN
NAME
FUNCTION
78
RLINK
Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits
(ZBTSI) one RCLK before the start of a frame. See Section 16 for details.
79
RLCLK
Receive Link Clock. A 4kHz or 2 kHz (ZBTSI) clock for the RLINK output.
82
RCLK
Receive Clock. 1.544MHz clock that is used to clock data through the receive side
framer.
92
RCHCLK
Receive Channel Clock. A 192kHz clock that pulses high during the LSB of each
channel. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
1
RCHBLK
Receive Channel Block. A user-programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications
where not all T1 channels are used, such as Fractional T1, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications,
for external per-channel loopback, and for per-channel conditioning. See Section 10 for
details.
95
RSER
Receive Serial Data. Received NRZ serial data. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated on the rising edges of
RSYSCLK when the receive side elastic store is enabled.
98
RSYNC
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which
identifies either frame (RCR2.4 = 0) or multiframe (RCR2.4 = 1) boundaries. If set to
output frame boundaries then via RCR2.5, RSYNC can also be set to output double-
wide pulses on signaling frames. If the receive side elastic store is enabled via CCR1.2,
then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section 16 for details.
97
RFSYNC
Receive Frame Sync. An extracted 8kHz pulse 1 RCLK wide is output at this pin that
identifies frame boundaries.
96
RMSYNC
Receive Multiframe Sync. Only used when the receive side elastic store is enabled. An
extracted pulse, 1 RSYSCLK wide, is output at this pin, which identifies multiframe
boundaries. If the receive side elastic store is disabled, then this output will output
multiframe boundaries associated with RCLK.
85
RDATA
Receive Data. Updated on the rising edge of RCLK with the data out of the receive side
framer.
100
RSYSCLK
Receive System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic
store function is enabled. Should be tied low in applications that do not use the elastic
store. Can be burst at rates up to 8.192MHz.
94
RSIG
Receive Signaling Output. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive side elastic store is disabled. Updated on the rising
edges of RSYSCLK when the receive side elastic store is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2152L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2152L-ES | 制造商:DALL 功能描述: |
| DS2152LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2152LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2153DK | 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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