參數(shù)資料
型號: DS2152L+
廠商: Maxim Integrated Products
文件頁數(shù): 67/97頁
文件大?。?/td> 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2152
7 of 97
1.2 Functional Description
The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins
of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received
signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -36dB, which allows the device to operate on cables up to 6000 feet in length. The receive side
framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including
carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered T1 data
stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048MHz clock or a 1.544MHz clock. The RSYSCLK
can be a bursty clock with speeds up to 8.192MHz.
The transmit side of the DS2152 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2152 will drive the T1 line from the
TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short
haul (DSX-1) lines.
1.3 Reader’s Note
This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125
s frame,
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. Each channel is made up of 8 bits that are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the
following abbreviations are used:
D4
Superframe (12 frames per multiframe) Multiframe Structure
SLC-96
Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark)
ESF
Extended Superframe (24 frames per multiframe) Multiframe Structure
B8ZS
Bipolar with 8 0 Substitution
CRC
Cyclical Redundancy Check
Ft
Terminal Framing Pattern in D4
Fs
Signaling Framing Pattern in D4
FPS
Framing Pattern in ESF
MF
Multiframe
BOC
Bit Oriented Code
HDLC
High Level Data Link Control
FDL
Facility Data Link
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