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| 型號： | DS2154LN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/87頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 1CHIP 5V ENH 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | E1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
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DS2154
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PIN
NAME
FUNCTION
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high
when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5
s.
6
RCL
Receive Carrier Loss. Set high when the line interface detects a loss of carrier. Note: A
test mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in
place of detection at RTIP and RRING.
93
RSIGF
Receive Signaling Freeze. Set high when the signaling data is frozen via either
automatic or manual intervention. Used to alert downstream equipment of the condition.
3
8MCLK
8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at
the RCLK pin.
91
RPOSO
Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RPOSI.
90
RNEGO
Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RNEGI.
89
RCLKO
Receive Clock Output. Buffered recovered clock from the E1 line. This pin is normally
tied to RCLKI.
86
RPOSI
Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
87
RNEGI
Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
88
RCLKI
Receive Clock Input. Clock used to clock data through the receive side framer. This pin
is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC
pin high. RCLKI must be present for the parallel control port to operate properly.
2.3 Parallel Control Port Pins
PIN
NAME
FUNCTION
25
INT
Interrupt. Flags host controller during conditions and change of conditions defined in
the Status Registers 1 and 2. Active-low, open-drain output.
14
TEST
Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel
control port). Set low for normal operation. Useful in board-level testing.
55
MUX
Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select
multiplexed bus operation.
56–65
D0–D7/
AD0–AD7
Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as
the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
66–72
A0–A6
Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
11
BTS
Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus
timing. This pin controls the function of the RD ( DS ), ALE(AS), and WR (R/ W ) pins.
If BTS = 1, then these pins assume the function listed in parentheses.
74
RD(DS)
Read Input (Data Strobe). RD and DS are active-low signals when MUX = 1. DS is
active high when MUX = 0. See the bus timing diagrams.
75
CS
Chip Select. Must be low to read or write to the device. CS is an active-low signal.
73
ALE(AS)
A7 or Address Latch Enable (Address Strobe). In nonmultiplexed bus operation
(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),
serves to demultiplex the bus on a positive-going edge.
77
WR(R/W)
Write Input (Read/Write). WR is an active-low signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2154LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LNA2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LNA2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LND2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LND2+ | 制造商:Maxim Integrated Products 功能描述:ENHANCED E1 SCT LQFP REVD2 IND LF - Rail/Tube |
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