參數(shù)資料
型號: DS21552LN
廠商: Maxim Integrated Products
文件頁數(shù): 109/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
73 of 137
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL
POSITION
NAME AND DESCRIPTION
RABT
RHIR.7
Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a
row.
RCRCE
RHIR.6
CRC Error. Set when the CRC checksum is in error.
ROVR
RHIR.5
Overrun. Set when the HDLC controller has attempted to write a byte into an already full
receive FIFO.
RVM
RHIR.4
Valid Message. Set when the HDLC controller has detected and checked a complete
HDLC packet.
REMPTY
RHIR.3
Empty. A real–time bit that is set high when the receive FIFO is empty.
POK
RHIR.2
Packet OK. Set when the byte available for reading in the receive FIFO is the last byte of
a valid message (and hence no abort was seen, no overrun occurred, and the CRC was
correct).
CBYTE
RHIR.1
Closing Byte. Set when the byte available for reading in the receive FIFO is the last byte
of a message (whether the message was valid or not).
OBYTE
RHIR.0
Opening Byte. Set when the byte available for reading in the receive FIFO is the first byte
of a message.
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
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