參數(shù)資料
型號: DS21552LN
廠商: Maxim Integrated Products
文件頁數(shù): 84/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內(nèi)回路代碼發(fā)生器和檢測器
DS21352/DS21552
50 of 137
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
RSC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
IMR2.7
Receive Multiframe.
0 = interrupt masked
1 = interrupt enabled
TMF
IMR2.6
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
SEC
IMR2.5
One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDL
IMR2.4
Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
TFDL
IMR2.3
Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
RMTCH
IMR2.2
Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
RAF
IMR2.1
Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
RSC
IMR2.0
Receive Signaling Change.
0 = interrupt masked
1 = interrupt enabled
8. ERROR COUNT REGISTERS
There are a set of three counters that record bipolar violations, excessive zeros, errors in the CRC6 code
words, framing bit errors, and number of multiframes that the device is out of receive synchronization.
Each of these three counters are automatically updated on either one second boundaries (CCR3.2=0) or
every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence, these registers
contain performance data from either the previous second or the previous 42 ms. The user can use the
interrupt from the one second timer to determine when to read these registers. The user has a full second
(or 42 ms) to read the counters before the data is lost. All three counters will saturate at their respective
maximum counts and they will not rollover (note: only the Line Code Violation Count Register has the
potential to over-flow but the bit error would have to exceed 10E-2 before this would occur).
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