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參數(shù)資料
| 型號(hào)： | DS21552LN |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 67/137頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX T1 1-CHIP 5V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | E1，HDLC，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 包括： | DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測(cè)器 |
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DS21352/DS21552
35 of 137
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
(LSB)
TESE
ODF
RSAO
TSCLKM
RSCLKM
RESE
PLB
FLB
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR1.7
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
ODF
CCR1.6
Output Data Format.
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
RSAO
CCR1.5
Receive Signaling All One’s. This bit should not be enabled if hardware signaling is
being utilized. See Section 10 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKM
CCR1.4
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz or IBO enabled (see section 20 for details on IBO
function)
RSCLKM
CCR1.3
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz or IBO enabled (see section 20 for details on IBO
function)
RESE
CCR1.2
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLB
CCR1.1
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLB
CCR1.0
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
6.3 PAYLOAD LOOPBACK
Payload Loopback When CCR1.1 is set to a one, the DS21352/552 will be forced into Payload LoopBack
(PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled
also in D4 framing applications. In a PLB situation, the DS21352/552 will loop the 192 bits of pay-load
data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pat-
tern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS21352/552.
When PLB is enabled, the following will occur:
1. data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK
2. all of the receive side signals will continue to operate normally
3. the TCHCLK and TCHBLK signals are forced low
4. data at the TSER, TDATA, and TSIG pins is ignored
5. the TLCLK signal will become synchronous with RCLK instead of TCLK.
6.4 FRAMER LOOPBACK
When CCR1.0 is set to a one, the DS21352/552 will enter a Framer LoopBack (FLB) mode. This
loopback is useful in testing and debugging applications. In FLB, the DS21352/552 will loop data from
the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all one’s code will be transmitted at TPOSO and TNEGO
2. Data at RPOSI and RNEGI will be ignored
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21552LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554 | 制造商:Maxim Integrated Products 功能描述: |
| DS21554G | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21554GN | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21554L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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