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參數(shù)資料
| 型號： | DS21FF42 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER T1 4X4 16CH 300-BGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 控制器類型： | T1 調(diào)幀器 |
| 接口： | 并行/串行 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 300mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 300-BBGA |
| 供應(yīng)商設(shè)備封裝： | 300-PBGA（27x27） |
| 包裝： | 管件 |
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DS21FT42/DS21FF42
21 of 114
Signal Name:
RLCLK
Signal Description:
Receive Link Clock
Signal Type:
Output
A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output. This signal is not bonded out in the
DS21FF42/DS21FT42.
Signal Name:
RCHCLK
Signal Description:
Receive Channel Clock
Signal Type:
Output
A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS =
1 (DS21Q41 emulation). This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
RCHBLK
Signal Description:
Receive Channel Block
Signal Type:
Output
A user programmable output that can be forced high or low during any of the 24 T1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all T1 channels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications,
for external per–channel loopback, and for per–channel conditioning. See Section 16 for details.
Signal Name:
RSER
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
RSYNC
Signal Description:
Receive Sync
Signal Type:
Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4 = 0) or
multiframe (RCR2.4 = 1) boundaries. If set to output frame boundaries then via RCR2.5, RSYNC can
also be set to output double–wide pulses on signaling frames. If the receive side elastic store is enabled
via CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe
boundary pulse is applied. See Section 24 for details.
Signal Name:
RFSYNC
Signal Description:
Receive Frame Sync
Signal Type:
Output
An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. This
signal is not bonded out in the DS21FF42/DS21FT42.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FF42+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF42N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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