參數(shù)資料
型號: DS21FF42
廠商: Maxim Integrated Products
文件頁數(shù): 90/114頁
文件大小: 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
77 of 114
The CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use
the DS21Q42 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 19.3]
(MSB)
(LSB)
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
TFDL7
TFDL.7
MSB of the FDL code to be transmitted
TFDL0
TFDL.0
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
19.3 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the these message fields
via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of
how to implement a SLC–96
19.
PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION
Each framer in the DS21Q42 has the ability to generate and detect a repeating bit pattern that is from one
to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit
Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1
bits in the In–Band Code Control (IBCC) register. Once this is accomplished, the pattern will be
transmitted as long as the TLOOP control bit (CCR3.1) is enabled. Normally (unless the transmit
formatter is programmed to not insert the F–bit position) the framer will overwrite the repeating pattern
once every 193 bits to allow the F–bit position to be sent. See Figure 24-15 for more details. As an
example, if the user wished to transmit the standard “l(fā)oop up” code for Channel Service Units which is a
repeating pattern of ...10000100001... then 80h would be loaded into TDR and the length would set to 5
bits.
Each framer can detect two separate repeating patterns to allow for both a “l(fā)oop up” code and a “l(fā)oop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of
each pattern will be selected via the IBCC register. The framer will detect repeating pattern codes in both
framed and unframed circumstances with bit error rates as high as 10**–2. The code detector has a
nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status
bit (LUP at SR1.7 and LDN at SR1.6) will be set to a one. Normally codes are sent for a period of 5
seconds. It is recommend that the software poll the framer every 100 ms to 1000 ms until 5 seconds has
elapsed to insure that the code is continuously present.
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