參數(shù)資料
型號: DS21Q42T
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 62/119頁
文件大小: 1309K
代理商: DS21Q42T
DS21Q42
47 of 119
MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)
Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of
sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of
Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the
MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1)
conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft
framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the
MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)
conditions.
See Table 8-3 for a detailed description of what the MOSCR is capable of counting.
MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1
(Address = 25 Hex)
MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2
(Address = 27 Hex)
(MSB)
(LSB)
MOS/
FB11
MOS/
FB10
MOS/
FB9
MOS/
FB8
(note 1)
MOSCR
1
MOS/
FB7
MOS/
FB6
MOS/
FB5
MOS/
FB4
MOS/
FB3
MOS/
FB2
MOS/
FB1
MOS/
FB0
MOSCR
2
SYMBOL
POSITION
NAME AND DESCRIPTION
MOS/FB11
MOSCR1.7
MSB of the 12–Bit Multiframes Out of Sync or F–Bit Error
Count (note #2)
MOS/FB0
MOSCR2.0
LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error
Count (note #2)
Notes:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of
sync (RCR2.0=1)
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