參數(shù)資料
型號(hào): DS21Q42T
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 82/119頁
文件大?。?/td> 1309K
代理商: DS21Q42T
DS21Q42
65 of 119
HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HIMR.7
Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
RPE
HIMR.6
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
RPS
HIMR.5
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
RHALF
HIMR.4
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
RNE
HIMR.3
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
THALF
HIMR.2
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
TNF
HIMR.1
Transmit FIFO Not Full.
0 = interrupt masked
1 = interrupt enabled
TMEND
HIMR.0
Transmit Message End.
0 = interrupt masked
1 = interrupt enabled
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = 03 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL
POSITION
NAME AND DESCRIPTION
RABT
RHIR.7
Abort Sequence Detected. Set whenever the HDLC controller
sees 7 or more ones in a row.
RCRCE
RHIR.6
CRC Error. Set when the CRC checksum is in error.
ROVR
RHIR.5
Overrun. Set when the HDLC controller has attempted to write
a byte into an already full receive FIFO.
RVM
RHIR.4
Valid Message. Set when the HDLC controller has detected and
checked a complete HDLC packet.
REMPTY
RHIR.3
Empty. A real–time bit that is set high when the receive FIFO is
empty.
相關(guān)PDF資料
PDF描述
DS21Q43AT DATACOM, FRAMER, PQFP128
DS21Q44T DATACOM, FRAMER, PQFP128
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
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