參數(shù)資料
型號: DS21Q42T
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 97/119頁
文件大?。?/td> 1309K
代理商: DS21Q42T
DS21Q42
79 of 119
19.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
19.1 Description
The DS21Q42 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and
IDCODE. See Figure 19-1 for a block diagram. The DS21Q42 contains the following items, which meet
the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). Details
on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE
1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Boundary Scan Architecture Figure 19-1
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI
JTMS
JTCLK
JTRST
JTDO
+V
Test Access Port
Controller
MUX
10K
Select
Output Enable
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