參數(shù)資料
型號： DS21Q48
廠商： Maxim Integrated Products
文件頁數(shù)： 29/73頁
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 QUAD 5V 144-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 144-BBGA
供應(yīng)商設(shè)備封裝： 144-PBGA（17x17）
包裝： 管件
DS2148/DS21Q48
35 of 73
Table 5-1. Received Alarm Criteria
ALARM
E1/T1
SET CRITERIA
CLEAR CRITERIA
RUA1
E1
Less than two zeros in two
frames (512 bits)
More than two zeros in two
frames (512 bits)
RUA1
T1
Over a 3ms window, five or less
zeros are received
Over a 3ms window, six or more
zeros are received
RCL1
E1
255 (or 2048)2 consecutive zeros
received
(G.775)
In 255 bit times, at least 32 ones
are received
RCL1
T1
192 (or 1544)2 consecutive zeros
are received
14 or more ones out of 112
possible bit positions are
received starting with the first
one received
NOTES:
1) Receive carrier loss (RCL) is also known as loss-of-signal (LOS) or Red Alarm in T1.
2) See CCR1.5 for details.
SR (06H): STATUS REGISTER
(MSB)
(LSB)
LUP
LDN
LOTC
RUA1
RCL
TCLE
TOCD
PRBSD
SYMBOL
POSITION
DESCRIPTION
LUP
(latched)
SR.7
Loop Up Code Detected. Set when the loop up code defined in
registers RUPCD1 and RUPCD2 is being received. See Section
4 for details.
LDN
(latched)
SR.6
Loop Down Code Detected. Set when the loop down code
defined in registers RDNCD1 and RDNCD2 is being received.
See Section 4 for details.
LOTC
(real time)
SR.5
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for 5
sec (±2sec). Will force the LOTC pin high.
RUA1
(latched)
SR.4
Receive Unframed All Ones. Set when an unframed all ones
code is received at RRING and RTIP. See Table 5-1 for details.
RCL
(latched)
SR.3
Receive Carrier Loss. Set when a receive carrier loss condition
exists at RRING and RTIP. See Table 5-1 for details.
TCLE
(real time)
SR.2
Transmit Current Limit Exceeded. Set when the 50mA
(RMS) current limiter is activated whether the current limiter is
enabled or not.
TOCD
(real time)
SR.1
Transmit Open Circuit Detect. Set when the device detects
that the TTIP and TRING outputs are open circuited.
PRBSD
(real time)
SR.0
PRBS Detect. Set when the receive-side detects a 215-1 (E1) or
a 220-1 (T1) Pseudo Random Bit Sequence (PRBS).
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