參數(shù)資料
型號: DS21Q48
廠商: Maxim Integrated Products
文件頁數(shù): 31/73頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 QUAD 5V 144-BGA
標準包裝: 90
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 144-BBGA
供應(yīng)商設(shè)備封裝: 144-PBGA(17x17)
包裝: 管件
DS2148/DS21Q48
37 of 73
RIR1 (08H): RECEIVE INFORMATION REGISTER 1
(MSB)
(LSB)
ZD
16ZD
HBD
RCLC
RUA1C
JALT
N/A
SYMBOL
POSITION
DESCRIPTION
ZD
(latched)
RIR1.7
Zero Detect. Set when a string of at least four (ETS = 0) or
eight (ETS = 1) consecutive zeros (regardless of the length of
the string) have been received. Will be cleared when read.
16ZD
(latched)
RIR1.6
Sixteen Zero Detect. Set when at least 16 consecutive zeros
(regardless of the length of the string) have been received. Will
be cleared when read.
HBD
(latched)
RIR1.5
HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or
B8ZS (ETS = 1) code word is detected independent of whether
the receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be
cleared when read. Useful for automatically setting the line
coding.
RCLC
(latched)
RIR1.4
Receive Carrier Loss Clear. Set when the RCL alarm has met
the clear criteria defined in Error! Reference source not
found.. Will be cleared when read.
RUA1C
(latched)
RIR1.3
Receive Unframed All Ones Clear. Set when the unframed all
ones signal is no longer detected. Will be cleared when read.
JALT
(latched)
RIR1.2
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its useful limit. Will be cleared
when read. Useful for debugging jitter attenuation operation.
N/A
RIR1.1
Not Assigned. Could be any value when read.
N/A
RIR1.0
Not Assigned. Could be any value when read.
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