參數(shù)資料
型號(hào): DS21Q50LN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 41/87頁(yè)
文件大?。?/td> 0K
描述: IC TRANSCEIVER E1 QD IND 100LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
DS21Q50
46 of 87
9. SYSTEM CLOCK INTERFACE
A single system clock interface (SCI) is common to the four DS21Q50 transceivers. The SCI allows any
one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s
are used to build an N port system, the SCI allows any one of the N ports to be the master. The selected
reference is then distributed to the other DS21Q50s through the REFCLK pin. The REFCLK pin acts as
an output on the DS21Q50, which has been selected to provide the reference clock from one of its four
receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input by writing
0s to the SCSx bits. The reference clock is also passed to the clock synthesizer PLL to generate a
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. This clock can then be used with the IBO
function to merge up to eight E1 lines onto a single high-speed PCM bus. If the master E1 port fails
(enters a receive carrier-loss condition), that port automatically switches to the clock present on the
MCLK pin. Therefore, MCLK acts as the backup source of master clock. The host can then find and
select a functioning E1 port as the master. Because the selected port’s clock is passed to the other
DS21Q50s in a multiple device configuration, one DS21Q50’s synthesizer can always be the source of
the high-speed clock. This allows smooth transitions when clock-source switching occurs. The SCI
control register exists in transceiver 1 only (TS0, TS1 = 0).
Register Name:
SCICR
Register Description:
System Clock Interface Control Register (Note: This register is valid
only for transceiver 1 (TS0 = 0, TS1 = 0).
Register Address:
1D Hex
Bit
7
6
5
4
3
2
1
0
Name
AJACKE
BUCS
SOE
CSS1
CSS0
SCS2
SCS1
SCS0
NAME
BIT
FUNCTION
AJACKE
7
AJACK Enable. This bit enables the alternate jitter attenuator.
BUCS
6
Backup Clock Select. Selects which clock source to switch to automatically during a loss-
of-transmit clock event.
0 = During an LOTC event, switch to MCLK
1 = During an LOTC event, switch to system reference clock
SOE
5
Synthesizer Output Enable
0 = 2/4/8/16MCK pin in high-Z mode
1 = 2/4/8/16MCK pin active
CSS1
4
Clock Synthesizer Select Bit 1 (Table 9-2)
CSS0
3
Clock Synthesizer Select Bit 0 (Table 9-2)
SCS2
2
System Clock Select Bit 2 (Table 9-1)
SCS1
1
System Clock Select Bit 1 (Table 9-1)
SCS0
0
System Clock Select Bit 0 (Table 9-1)
相關(guān)PDF資料
PDF描述
DS21Q55 IC TXRX QUAD T1/E1/J1 SCT 256BGA
DS21Q59LN+ IC TXRX E1 QUAD 100-LQFP
DS21S07AS+T&R IC TERMINATOR SCSI 16-SOIC
DS21T05Z/T&R IC TERMINATOR SCSI 150MIL 16SOIC
DS21T07S+T&R IC TERMINATOR SCSI 16-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q50LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q50L-W+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q50N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
DS21Q55 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS21Q552 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray