DS21Q55 Quad T1/E1/J1 Transceiver
3 of 237
12.1.1
T1 Operation..............................................................................................80
12.1.2
E1 Operation..............................................................................................80
12.2
P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR).........................................82
12.2.1
T1 Operation..............................................................................................82
12.2.2
E1 Operation..............................................................................................82
12.3
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR).........................................83
12.3.1
T1 Operation..............................................................................................83
12.3.2
E1 Operation..............................................................................................83
12.4
E-B
IT
C
OUNTER
(EBCR)..................................................................................84
13.
DS0 MONITORING FUNCTION ..................................................................................................85
14.
SIGNALING OPERATION...........................................................................................................87
R
ECEIVE
S
IGNALING
........................................................................................87
14.1.1
Processor-Based Signaling........................................................................87
14.1.2
Hardware-Based Receive Signaling...........................................................88
14.2
T
RANSMIT
S
IGNALING
......................................................................................93
14.2.1
Processor-Based Mode..............................................................................93
14.2.2
Software Signaling Insertion-Enable Registers, E1 CAS Mode ..................97
14.2.3
Software Signaling Insertion-Enable Registers, T1 Mode...........................99
14.2.4
Hardware-Based Mode ..............................................................................99
15.
PER-CHANNEL IDLE CODE GENERATION............................................................................100
15.1
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
...........................................................101
16.
CHANNEL BLOCKING REGISTERS........................................................................................105
14.1
17.
ELASTIC STORES OPERATION..............................................................................................108
R
ECEIVE
S
IDE
...............................................................................................111
17.1.1
T1 Mode...................................................................................................111
17.1.2
E1 Mode...................................................................................................111
17.2
T
RANSMIT
S
IDE
.............................................................................................111
17.2.1
T1 Mode...................................................................................................112
17.2.2
E1 Mode...................................................................................................112
17.3
E
LASTIC
S
TORES
I
NITIALIZATION
.....................................................................112
17.4
M
INIMUM
D
ELAY
M
ODE
..................................................................................112
18.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................113
17.1
19.
T1 BIT-ORIENTED CODE (BOC) CONTROLLER ....................................................................114
T
RANSMIT
BOC.............................................................................................114
19.1.1
Example: Transmit a BOC........................................................................114
19.2
R
ECEIVE
BOC...............................................................................................114
19.2.1
Example: Receive a BOC.........................................................................114
20.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY).........................117
20.1
M
ETHOD
1: H
ARDWARE
S
CHEME
....................................................................117
20.2
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
..............117
20.3
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
........120
21.
HDLC CONTROLLERS.............................................................................................................130
21.1
B
ASIC
O
PERATION
D
ETAILS
............................................................................130
21.2
HDLC C
ONFIGURATION
.................................................................................130
21.2.1
FIFO Control ............................................................................................134
19.1