DS21Q55 Quad T1/E1/J1 Transceiver
4 of 237
21.3
21.3.1
Receive....................................................................................................135
21.3.2
Transmit...................................................................................................137
21.3.3
FIFO Information......................................................................................142
21.3.4
Receive Packet-Bytes Available...............................................................142
21.3.5
HDLC FIFOs............................................................................................143
21.4
R
ECEIVE
HDLC C
ODE
E
XAMPLE
....................................................................144
21.5
L
EGACY
FDL S
UPPORT
(T1 M
ODE
)................................................................144
21.5.1
Overview..................................................................................................144
21.5.2
Receive Section.......................................................................................144
21.5.3
Transmit Section......................................................................................146
21.6
D4/SLC-96 O
PERATION
.................................................................................146
22.
LINE INTERFACE UNIT (LIU)...................................................................................................147
22.1
LIU O
PERATION
.............................................................................................147
22.2
R
ECEIVER
.....................................................................................................147
22.2.1
Receive Level Indicator and Threshold Interrupt ......................................148
22.2.2
Receive G.703 Synchronization Signal (E1 Mode)...................................148
22.2.3
Monitor Mode...........................................................................................148
22.3
T
RANSMITTER
................................................................................................149
22.3.1
Transmit Short-Circuit Detector/Limiter ....................................................149
22.3.2
Transmit Open-Circuit Detector................................................................149
22.3.3
Transmit BPV Error Insertion....................................................................149
22.3.4
Transmit G.703 Synchronization Signal (E1 Mode)..................................149
22.4
MCLK P
RESCALER
........................................................................................150
22.5
J
ITTER
A
TTENUATOR
......................................................................................150
22.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
...........................................................150
22.7
LIU C
ONTROL
R
EGISTERS
..............................................................................151
22.8
R
ECOMMENDED
C
IRCUITS
..............................................................................160
22.9
C
OMPONENT
S
PECIFICATIONS
........................................................................162
23.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION.......................166
HDLC M
APPING
............................................................................................135
24.
BERT FUNCTION......................................................................................................................173
S
TATUS
.........................................................................................................173
M
APPING
.......................................................................................................173
BERT R
EGISTER
D
ESCRIPTIONS
....................................................................175
BERT R
EPETITIVE
P
ATTERN
S
ET
...................................................................179
BERT B
IT
C
OUNTER
......................................................................................180
BERT E
RROR
C
OUNTER
................................................................................181
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)..............................................183
N
UMBER
-
OF
-E
RRORS
R
EGISTERS
..................................................................185
25.1.1
Number-of-Errors Left Register................................................................186
INTERLEAVED PCM BUS OPERATION (IBO).........................................................................187
26.1
C
HANNEL
I
NTERLEAVE
...................................................................................187
26.2
F
RAME
I
NTERLEAVE
.......................................................................................187
27.
EXTENDED SYSTEM INFORMATION BUS (ESIB)..................................................................190
24.1
24.2
24.3
24.4
24.5
24.6
25.
25.1
26.
28.
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER.....................................................194
29.
FRACTIONAL T1/E1 SUPPORT...............................................................................................195