參數(shù)資料
型號: DS26503LN+
廠商: Maxim Integrated Products
文件頁數(shù): 31/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: BITS 元件,多路復用器
PLL:
主要目的: T1/E1
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
16 of 122
4.4 Controller Interface
NAME
TYPE
FUNCTION
INT/
JACKS0
I/O
Active-Low Interrupt/Jitter Attenuator Clock Select 0
INT: Flags host controller during events, alarms, and conditions defined in the
status registers. Active-low open-drain output.
JACKS0: Hardware Mode: Jitter Attenuator Clock Select 0. Set this pin high
for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or
16.382MHz signal is applied at MCLK.
TMODE1
I
Transmit Mode Select 1. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
TMODE2
I
Transmit Mode Select 2. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
TSTRST
I
Three-State Control and Device Reset. A dual-function pin. A zero-to-one
transition issues a hardware reset to the DS26503 register set. Configuration
register contents are set to the default state. Leaving TSTRST high three-states
all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful for in-board level testing.
BIS[1:0]
I
Processor Interface Mode Select 1, 0. These bits select the processor
interface mode of operation.
BIS[1:0] : 00 = Parallel Port Mode (Multiplexed)
01 = Parallel Port Mode (Nonmultiplexed)
10 = Serial Port Mode
11 = Hardware Mode
AD[7]/
RITD
I/O
Data Bus D[7] or Address/Data Bus AD[7]/Receive Internal Termination
Disable
A[7]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[7].
AD[7]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[7].
RITD: In Hardware Mode (BIS[1:0] = 11), internal receive termination is
disabled when RITD = 1.
AD[6]/
TITD
I/O
Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal Termination
Disable
A[6]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[6].
AD[6]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[6].
TITD: In Hardware Mode (BIS[1:0] = 11), internal transmit termination is
disabled when TITD = 1.
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