參數資料
型號: DS26503LN+
廠商: Maxim Integrated Products
文件頁數: 61/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: BITS 元件,多路復用器
PLL:
主要目的: T1/E1
輸入: 時鐘
輸出: 時鐘
電路數: 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
43 of 122
Register Name:
T1TCR2
Register Description:
T1 Transmit Control Register 2
Register Address:
06h
Bit #
7
6
5
4
3
2
1
0
Name
TB8ZS
TFSE
FBCT2
FBCT1
TD4YM
TB7ZS
Default
0
1
0
HW
Mode
HBE
PIN 55
1
0
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS)
0 = no stuffing occurs
1 = bit 7 forced to a 1 in channels with all 0s
Bits 1 and 5: Unused, must be set = 0 for proper operation.
Bit 2: Transmit-Side D4 Yellow Alarm Select (TD4YM)
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4
framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of frame (loss of
synchronization).
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS
(ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 6: Transmit Fs-Bit Insertion Enable (TFSE). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to
source the Fs pattern from the TFDL register. In all other modes this bit must be set = 0.
0 = Fs-bit insertion disabled
1 = Fs-bit insertion enabled
Bit 7: Transmit B8ZS Enable (TB8ZS)
0 = B8ZS disabled
1 = B8ZS enabled
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