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| 型號： | DS28CM00R-A00+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 0K |
| 描述： | IC SILICON SERIAL NUMBER SOT23-5 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 硅序列號 |
| 應(yīng)用： | PCB，網(wǎng)絡(luò)節(jié)點(diǎn)，設(shè)備識別/注冊 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | DS28CM00R-A00+TDKR |
DS28CM00: IC/SMBus Silicon Serial Number
3 of 9
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC ≥ 2.7V
0.3
0.9
VCC ≥ 2.0V
0.3
1.1
Data Hold Time (Notes 9, 10)
tHD:DAT
VCC < 2.0V
0.3
1.7
s
Data Setup Time
tSU:DAT
(Notes 8, 11)
100
ns
Setup Time for STOP Condition
tSU:STO
(Note 8)
0.6
s
Bus Free Time Between a
STOP and START Condition
tBUF
(Note 8)
1.3
s
Capacitive Load for Each Bus
Line
Cb
(Notes 4, 8)
400
pF
Note 1:
Specifications at -40
°C are guaranteed by design and characterization only and not production tested.
Note 2:
All values are referred to VIHmin and VILmax levels.
Note 3:
The maximum specification value is guaranteed by design, not production tested.
Note 4:
Not production tested. Guaranteed by design or characterization.
Note 5:
CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I
2C-Bus Specification v2.1 are allowed.
Note 6:
The DS28CM00 does not obstruct the SDA and SCL lines if VCC is switched off.
Note 7:
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL
stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it
has sensed a STOP condition.
Note 8:
System Requirement
Note 9:
The DS28CM00 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10:
The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL
signal.
Note 11:
A Fast-mode IC-bus device can be used in a standard-mode IC-bus system, but the requirement
tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode IC-bus specification) before the SCL line is released.
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
SCL
Serial interface clock input; must be tied to VCC through a pullup resistor. 5V tolerant input
over 1.62V to 5.25V VCC range.
2
GND
Ground supply for the device.
3
SDA
Serial interface bi-directional data line; must be tied to VCC through a pullup resistor. 5V
tolerant input/output over 1.62V to 5.25V VCC range.
4
N.C.
Not Connected
5
VCC
Power Supply Input
OVERVIEW
The DS28CM00 consists of a serial interface which provides access to a unique 64-bit Registration number and a
Control Register, as shown in the block diagram in Figure 1. The device communicates with a host processor
through its SMBus compatible IC bus interface in standard-mode or in fast-mode. Since the network address of
the DS28CM00 is fixed, exactly one device can reside on a bus segment. The Registration Number and Control
Register are located in a linear 9-byte address space (Figure 2).
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