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| 型號： | DS28CM00R-A00+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SILICON SERIAL NUMBER SOT23-5 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 硅序列號 |
| 應(yīng)用： | PCB，網(wǎng)絡(luò)節(jié)點，設(shè)備識別/注冊 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標準包裝 |
| 其它名稱： | DS28CM00R-A00+TDKR |
DS28CM00: IC/SMBus Silicon Serial Number
7 of 9
Not Acknowledged by Slave
A slave device may be unable to receive or transmit data, e.g., because it is busy. As a SMBus-compatible device,
the DS28CM00 will always acknowledge its slave address. However, some time later the slave may refuse to
accept data, e.g., because of an invalid memory address or access mode, e. g. attempting to write to a ROM byte.
In this case the slave device will not acknowledge any of the bytes that it refuses and will leave SDA HIGH. After a
slave has failed to acknowledge, the master should generate a repeated START condition or a STOP condition
followed by a START condition to begin a new data transfer.
Not Acknowledged by Master
At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the
master does not acknowledge the last byte that it has received from the slave. In response, the slave releases
SDA, allowing the master to generate the STOP condition.
Figure 5. IC/SMBus Timing Diagram
SCL
SDA
STOP
START
tBUF
tHD:STA
tLOW
tR
tHD:DAT
tHIGH
tSU:DAT
Repeated
START
tSU:STA
tF
tHD:STA
tSP
tSU:STO
Spike
Suppression
NOTE: Timing is referenced to VILMAX and VIHMIN.
Read and Write
The DS28CM00 behaves like an IC memory device with an 9-byte memory map (Figure 2). The memory consists
of 8 bytes ROM and one byte SRAM, i. e., the Control Register. The ROM data cannot be changed.
To write to the DS28CM00, the master must access the device in write access mode, i.e., the slave address must
be sent with the direction bit set to 0. The next byte to be sent in write access mode is an address byte to set the
address pointer to a specific location. The DS28CM00 acknowledges any address between 00h and 08h. Write
attempts to the ROM are ignored and data received for these addresses is not acknowledged. However, the
address pointer increments after every full data byte transmitted by the master and rolls over from 08h to 00h after
a full data byte is written to address 08h.
To read from the DS28CM00, the master must access the device in read access mode, i.e., the slave address
must be sent with the direction bit set to 1. The address pointer determines the location from which the master will
start reading. The pointer is set when the DS28CM00 is accessed in write access mode, as described above. The
power-on default of the pointer is 00h. When reading from the device, the address pointer increments with every
data byte read. When the end of the memory is reached (address 08h), the address pointer wraps around to 00h.
To read from an arbitrary address, the master must first access the DS28CM00 in write access mode and specify a
new memory address. The address pointer remains unchanged if the device resets its communication interface
due to a bus timeout in SMBus mode.
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