參數(shù)資料
型號(hào): DS28CM00R-A00+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/9頁
文件大?。?/td> 0K
描述: IC SILICON SERIAL NUMBER SOT23-5
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 硅序列號(hào)
應(yīng)用: PCB,網(wǎng)絡(luò)節(jié)點(diǎn),設(shè)備識(shí)別/注冊(cè)
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: DS28CM00R-A00+TDKR
DS28CM00: IC/SMBus Silicon Serial Number
4 of 9
Figure 1. Block Diagram
SCL
SDA
ROM
Registration
Number
Control
Register
Serial
Interface
VCC
GND
Figure 2. Memory Map
ADDRESS
TYPE
ACCESS
DESCRIPTION
00h
ROM
Read
Device Family Code (70h)
01h
ROM
Read
Serial Number, bits 0 to 7
02h
ROM
Read
Serial Number, bits 8 to 15
03h
ROM
Read
Serial Number, bits 16 to 23
04h
ROM
Read
Serial Number, bits 24 to 31
05h
ROM
Read
Serial Number, bits 32 to 39
06h
ROM
Read
Serial Number, bits 40 to 47
07h
ROM
Read
CRC of Family Code and 48-bit Serial Number
08h
SRAM
R/W
Control Register
Unique Registration Number
Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the
family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at
address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the
polynomial X
8 + X5 + X4 + 1. Additional information about CRCs is available in Application Note 27. The ROM
Registration Number is not related to the IC slave address of the device.
Control Register
The Control Register at address 08h allows switching between IC mode and SMBus mode. Only the LS bit of this
register, referred to as the CM bit, has a function. The other 7 bits always read 0 and cannot be changed. When the
CM bit is set to 1 (power-on default), the device is in SMBus mode, which enables the bus timeout function. Setting
the CM bit to 0 puts the device in IC mode, where the timeout function is disabled. In SMBus mode, the serial
interface times out and is internally reset if SCL is stuck (high or low) or if SDA is stuck low for the duration of
tTIMEOUT or longer. This reset turns the SDA line into an input, ensuring that the device is ready to recognize a
communication start condition.
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
08h
0
CM
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