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參數(shù)資料
| 型號(hào)： | DS28CM00R-A00+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SILICON SERIAL NUMBER SOT23-5 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 硅序列號(hào) |
| 應(yīng)用： | PCB，網(wǎng)絡(luò)節(jié)點(diǎn)，設(shè)備識(shí)別/注冊(cè) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | DS28CM00R-A00+TDKR |
DS28CM00: IC/SMBus Silicon Serial Number
5 of 9
DEVICE OPERATION
Typically, the DS28CM00 is accessed after power-up to read the 64-bit Registration number, which may serve to
identify the object that the device is embedded in. Write access exists only to the Control Register. Read and write
access are controlled through the IC/SMBus serial interface. See section Read and Write for details.
Serial Communication Interface
General Characteristics
The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the
Standard-mode, up to 400kbps in the Fast-mode. The DS28CM00 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” The DS28CM00 is a slave device.
Slave Address/Direction Byte
To be individually accessed, each device must have a slave address that does not conflict with other devices on
the bus. The slave address to which the DS28CM00 responds is shown in Figure 3. The slave address is part of
the slave-address/direction byte. The last bit of the slave-address/direction byte (R/
W) defines the data direction.
When set to a 0, subsequent data will flow from master to slave (write access mode); when set to a 1, data will flow
from slave to master (read access mode).
Figure 3. DS28CM00 Slave Address
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
R/W
7-Bit Slave Address
Most Signi-
ficant Bit
Determines
Read or Write
IC/SMBus Protocol
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of bytes
transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line while
SCL is high will be interpreted as a START or a STOP. The protocol is illustrated in Figure 4. For detailed timing
references see Figure 5.
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