參數(shù)資料
型號: DS31256+
廠商: Maxim Integrated Products
文件頁數(shù): 176/183頁
文件大?。?/td> 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: HDLC 控制器
接口: 串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 500mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 管件
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DS31256 256-Channel, High-Throughput HDLC Controller
92 of 183
9.2.3 Free Queue
The host writes the 32-bit addresses of the available (free) data buffers and their associated packet
descriptors to the receive free queue. The descriptor space is indicated through a 16-bit pointer, which
the DMA uses along with the receive packet descriptor base address to find the exact 32-bit address of
the associated receive packet descriptor.
Figure 9-5. Receive Free-Queue Descriptor
dword 0
Free Data Buffer Address (32)
dword 1
Unused (16)
Free Packet Descriptor Pointer (16)
Note: The organization of the free queue is not affected by the enabling of Big Endian.
dword 0; Bits 0 to 31/Data Buffer Address. Direct 32-bit starting address of a free data buffer.
dword 1; Bits 0 to 15/Free Packet Descriptor Pointer. This 16-bit value is the offset from the receive descriptor
base address of the free descriptor space associated with the free data buffer in dword 0. Note: This is an index,
not an absolute address.
dword 1; Bits 16 to 31/Unused. Not used by the DMA. Can be set to any value by the host and is ignored by the
receive DMA.
The receive DMA reads from the receive free-queue descriptor circular queue which data buffers and
their associated descriptors are available for use by the DMA.
The receive free-queue descriptor is actually a set of two circular queues (Figure 9-6). There is one
circular queue that indicates where free large buffers and their associated free descriptors exist. There is
another circular queue that indicates where free small buffers and their associated free descriptors exist.
Large and Small Buffer Size Handling
Through the receive configuration-RAM buffer-size field, the DMA knows for a particular HDLC
channel whether the incoming packets should be stored in the large or the small free data buffers. The
host informs the DMA of the size of both the large and small buffers through the receive large and small
buffer size (RLBS/RSBS) registers. For example, when the DMA knows that data is ready to be written
onto the PCI bus, it checks to see if the data is to be sent to a large buffer or a small buffer, and then it
goes to the appropriate free-queue descriptor and pulls the next available free buffer address and free
descriptor pointer. If the host wishes to have only one buffer size, then the receive free queue small-
buffer start address is set equal to the receive free-queue end address. In the receive configuration RAM,
none of the active HDLC channels are configured for the small buffer size.
There are a set of internal addresses within the device to keep track of the addresses of the dual circular
queues in the receive free queue. These are accessed by the host and the DMA. On initialization, the host
configures all the registers shown in Table 9-E. After initialization, the DMA only writes to (changes)
the read pointers and the host only writes to the write pointers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31256+ 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256B 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC