參數(shù)資料
型號(hào): DS31256+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 45/183頁(yè)
文件大?。?/td> 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類(lèi)型: HDLC 控制器
接口: 串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 500mA
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 管件
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DS31256 256-Channel, High-Throughput HDLC Controller
139 of 183
10.2.2 Status Bits (PCMD0)
The upper word in the PCMD0 register is the status portion, which reports events as they occur. As previously
mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e.,
forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no effect. This
allows individual bits to be reset.
Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable
of running at 66MHz.
Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it
does not support user-definable features.
Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate
that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent.
Bit 24/PCI Parity Error Reported (PARR). This read/write bit is set to 1 when the device is a bus master and
detects or asserts the
PPERR signal when the PARC command bit is enabled. This bit can be reset (set to 0) by the
host by writing 1 to this bit.
0 = no parity errors have been detected
1 = parity errors detected
Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the
device to indicate that it is capable of the medium timing requirements for the
PDEVSEL signal.
Bit 27/Target Abort Initiated (TABT). This read-only bit is forced to 0 by the device since it does not terminate
a bus transaction with a target abort when the device is a target.
Bit 28/Target Abort Detected by Master (TABTM). This read/write bit is set to 1 when the device is a bus
master and it detects that a bus transaction has been aborted by the target with a target abort. This bit can be reset
(set to 0) by the host by writing 1 to this bit.
Bit 29/Master Abort (MABT). This read/write bit is set to 1 when the device is a bus master and the bus
transaction is terminated with a master abort (except for special cycle). This bit can be reset (set to 0) by the host
by writing 1 to this bit.
Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the
PSERR
signal. This bit can be reset (set to 0) by the host by writing 1 to this bit.
Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error
(even if parity is disabled through the PARC command bit). This bit can be reset (set to 0) by the host by writing 1
to this bit.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31256+ 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256B 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Industrial Control IC