參數(shù)資料
型號(hào)： DS31256+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/183頁(yè)
文件大?。?/td> 0K
描述： IC CTRLR HDLC 256-CHANNEL 256BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類(lèi)型： HDLC 控制器
接口： 串行
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 500mA
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-BBGA
供應(yīng)商設(shè)備封裝： 256-BGA（27x27）
包裝： 管件
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DS31256 256-Channel, High-Throughput HDLC Controller
104 of 183
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 16 to 28/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in
the data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes).
- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 29 to 31/Threshold Count. These bits keep track of the number of data buffers that have been
filled so that the receive DMA knows when, based on the host-controlled threshold, to write to the done queue.
000 = threshold count is 0 data buffers
001 = threshold count is 1 data buffer
010 = threshold count is 2 data buffers
011 = threshold count is 3 data buffers
100 = threshold count is 4 data buffers
101 = threshold count is 5 data buffers
110 = threshold count is 6 data buffers
111 = threshold count is 7 data buffers
Register Name:
RDMACIS
Register Description:
Receive DMA Channel Configuration Indirect Select
Register Address:
0770h
Bit #
7
6
5
4
3
2
1
0
Name
HCID7
HCID6
HCID5
HCID4
HCID3
HCID2
HCID1
HCID0
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
IAB
IARW
n/a
RDCW2
RDCW1
RDCW0
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
Bits 8 to 10/Receive DMA Configuration RAM Word Select Bits 0 to 2 (RDCW0 to RDCW2)
000 = lower word of dword 0
001 = upper word of dword 0
010 = lower word of dword 1
011 = upper word of dword 1
100 = lower word of dword 2 (only word that the host can write to)
101 = upper word of dword 2
110 = illegal state
111 = illegal state
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive DMA
configuration RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data
from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data
is ready to be read from the RDMAC register, the IAB bit is set to 0. When the host wishes to write data to the
internal receive DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to
take the data that is currently present in the RDMAC register and write it to the channel location indicated by the
HCID bits. When the device has completed the write, the IAB bit is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31256+ 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256B 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Industrial Control IC
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