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參數(shù)資料
| 型號(hào)： | DS31256+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 9/183頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
106 of 183
Table 9-G. Transmit DMA Main Operational Areas
DESCRIPTORS
FUNCTION
SECTION
Packet
A dedicated area of memory that describes the location and attributes of the
packet data.
Pending Queue
A dedicated area of memory that the host writes to inform the DMA that
packet data is queued and ready for transmission.
Done Queue
A dedicated area of memory that the DMA writes to inform the host that the
packet data has been transmitted.
Host Linking of Data Buffers
As previously mentioned, the data buffers are limited to a length of 8188 Bytes. If an outgoing packet
requires more memory space than the available data buffer contains, the host can link multiple data
buffers together to handle a packet length of any size. The host does this through the end-of-frame (EOF)
bit in the packet descriptor. Each data buffer has a one-to-one association with a packet descriptor. If the
host wants to link multiple data buffers together, the EOF bit is set to 0 in all but the last data buffer.
Figure 9-10 shows an example for HDLC channel 5 where the host has linked three data buffers
together. The transmit DMA knows where to find the next data buffer when the EOF bit is set to 0
through the next descriptor pointer field.
Host Linking of Packets (Packet Chaining)
The host also has the option to link multiple packets together in a chain. Through the chain valid (CV)
bit in the packet descriptor, the host can inform the transmit DMA that the next descriptor pointer field
contains the descriptor of another HDLC packet that is ready for transmission. The transmit DMA
ignores the CV bit until it sees EOF = 1, which indicates the end of a packet. If CV = 1 when EOF = 1,
this indicates to the transmit DMA that it should use the next descriptor pointer field to find the next
packet in the chain. Figure 9-12 shows an example of packet chaining. Each column represents a separate
packet chain. In column 1, three data buffers have been linked together by the host for packet #1, and the
host has created a packet chain by setting CV = 1 in the last descriptor of packet #1.
DMA Linking of Packets (Horizontal Link Listing)
The transmit DMA also has the ability to link packets together. Internally, the transmit DMA can store
up to two packet chains, but if the host places more packet chains into the pending queue, the transmit
DMA must begin linking these chains together externally. The transmit DMA does this by writing to
packet descriptors (Figure 9-12). If columns 1 and 2 were the only two packet chains queued for
transmission, then the transmit DMA would not need to link packet chains together, but as soon as
column 3 was queued for transmission, the transmit DMA had to store the third chain externally because
it had no more room internally. The transmit DMA links the packet chain in the third column to the one
in the second column by writing the first descriptor of the third chain in the next pending descriptor
pointer field of the first descriptor of the second column (it also sets the PV bit to 1). As shown in the
figure, this chaining was carried one step farther to link the fourth column to the third.
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| DS3141+ | IC FRAMER DS3/E3 SNGL 144CSBGA |
| DS31412N | IC 12CH DS3/3 FRAMER 349-BGA |
| DS3150TN | IC LIU T3/E3/STS-1 IND 48-TQFP |
| DS3154N+ | IC LIU DS3/E3/STS-1 QD 144CSBGA |
| DS3164+ | IC ATM/PACKET PHY QUAD 400-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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